PCB Via Types: Through-Hole, Blind, Buried, and Microvia — Complete Cost and Design Guide

The Via Selection Problem Most Engineers Get Wrong

Selecting via types for a PCB design should be a straightforward engineering decision, but in practice it is one of the most common sources of unnecessary cost in multilayer board fabrication. We review over 200 via structure specifications per week across customer designs ranging from simple 4-layer industrial controllers to complex 20-layer HDI networking platforms, and a consistent pattern emerges: approximately 40% of boards specified with blind or buried vias could achieve identical routing results using only through-hole vias with a more thoughtful stackup arrangement.

The opposite problem also exists. Engineers who default to through-hole vias on designs that genuinely need advanced via structures end up with boards that require additional layers to compensate for routing congestion, and those extra layers often cost more than the via upgrade would have. The key is matching the via type to the actual design requirements rather than defaulting to the simplest option or over-specifying based on what a competitor’s reference design uses.

This guide provides the specific cost data, lead time impacts, and decision thresholds you need to make this choice correctly. Every number cited comes from our production environment processing boards daily, not from theoretical calculations or outdated industry averages.

Understanding Via Anatomy: Barrel, Pad, Anti-Pad, and Stub

Before comparing via types, it helps to understand what all vias share structurally. Every plated via consists of three functional elements regardless of its span through the stackup.

The barrel is the copper-plated cylinder running through the drilled hole. Barrel plating thickness directly determines current-carrying capacity and reliability under thermal cycling. IPC-6012 Class 2 requires minimum 20 micrometers average barrel plating; Class 3 increases this to 25 micrometers. In our production, we target 25 micrometers minimum for all via types because the marginal plating cost is negligible while the reliability improvement under thermal stress is measurable.

The pad (or land) is the copper ring where the barrel meets a trace or plane on each connected layer. Pad diameter minus hole diameter gives you the annular ring, which must be maintained at or above minimum values to ensure reliable connection. Standard annular ring minimums range from 3.5 mil (89 micrometers) for outer layers to 3 mil (76 micrometers) for inner layers under IPC Class 2.

The anti-pad is the clearance hole in copper planes where the via passes through a layer it should not connect to. Anti-pad diameter must be large enough to prevent shorts to the plane (typically 8-10 mil larger than the drill diameter) but small enough to avoid creating excessive discontinuity in return current paths on nearby planes.

The stub is the portion of via barrel that extends beyond the last connected layer. On through-hole vias, the stub acts as an unterminated transmission line that creates resonant reflections at frequencies determined by the stub length. A 40 mil stub resonates near 18 GHz, which seems safely above most design frequencies until you consider that the quarter-wave resonance and its associated insertion loss notch appear at much lower frequencies and broadband reflections degrade signal edges starting well below the resonant frequency.

Through-Hole Vias: The Default That Handles Most Designs

Through-hole vias pass completely through the board from top surface to bottom surface, connecting all layers in between. They are mechanically drilled through the finished laminated stackup and electroplated in a single process step shared with all other plated holes on the board. This shared processing is why through-hole vias add zero incremental cost beyond the drilling and plating steps that the board already requires.

The mechanical drilling process for through-hole vias uses carbide drill bits ranging from 0.2mm (8 mil) minimum diameter up to 6.35mm for mounting holes and large power connections. Standard via drill sizes fall between 0.25mm and 0.35mm (10-14 mil), producing finished holes of 0.2mm to 0.3mm after plating. These dimensions accommodate most standard design rules and leave adequate annular ring at typical pad sizes of 0.5-0.6mm.

Aspect ratio is the primary manufacturing constraint for through-hole vias. Defined as board thickness divided by drilled hole diameter, the aspect ratio determines whether electroplating solution can reach the center of the barrel reliably. At 8:1 aspect ratio, plating uniformity begins degrading because the chemistry exchange rate at the barrel center cannot keep pace with plating at the entrance. Most fabricators quote up to 10:1 with standard chemistry, and some achieve 12:1 with specialized high-throw plating processes, but reliability drops measurably above 10:1.

For a standard 1.6mm thick board, this means the minimum reliable through-hole drill diameter is 0.2mm (giving 8:1 aspect ratio). On a 2.4mm board, the minimum increases to 0.3mm. These constraints rarely limit standard designs but become relevant on thick backplanes where engineers want small vias to preserve routing density.

From our production data, through-hole vias remain the correct choice for the vast majority of boards we manufacture. Specifically, they work well when the board has 8 or fewer layers (see our 8-layer PCB stackup design guide for detailed configurations), when BGA packages (if present) have pitch of 0.8mm or greater, when signal frequencies stay below 10 GHz without stringent stub requirements, and when routing density allows adequate channel width between via pads on all layers. Meeting all four conditions means through-hole vias will serve the design correctly at the lowest possible cost.

Blind Vias: Partial-Depth Connections for Dense BGA Fanout

Blind vias connect an outer layer (top or bottom) to one or more inner layers without penetrating the entire board thickness. The term “blind” refers to the fact that the via is visible from one board surface but invisible from the other. These structures free routing space on the layers they do not reach, making them valuable when escape routing from dense packages competes for channel space on inner layers.

The fabrication process for blind vias depends on the drill method. Laser-drilled blind vias (typically for depths up to one or two layers) use UV or CO2 lasers to ablate the dielectric and expose the target copper layer, followed by electroless and electrolytic copper plating. Mechanically drilled blind vias use controlled-depth drilling with a precision spindle that stops at a programmed depth, which requires careful calibration because the drill must penetrate through the target copper layer without damaging the layer below. Sequential lamination is a third approach: inner cores are drilled and plated as through-holes in a sub-assembly, then additional layers are laminated on top, converting what were through-holes into blind structures.

The cost impact of blind vias is substantial and predictable. On a standard 8-layer board, adding blind vias increases fabrication cost by 25-35% over the equivalent through-hole-only design. This premium reflects the sequential lamination process (additional press cycles), extra drilling operations, additional AOI inspection steps for sub-assemblies, and reduced panel yield from tighter registration requirements. At prototype quantities of 5-10 pieces, the absolute cost increase might be $5-8 per board. At production quantities of 500+ pieces, the per-unit adder narrows to $3-5 because setup costs amortize.

Lead time extension is the other critical factor. Blind vias add 3-5 working days to standard fabrication schedules because sequential lamination cannot be parallelized with outer-layer processing. The sub-assemblies must be completed, inspected, and approved before the next lamination step proceeds. On a board that would take 7 days with through-hole vias only, adding blind vias typically extends delivery to 10-12 days.

The practical trigger for specifying blind vias is BGA fanout routing. When a BGA package has pitch of 0.8mm or finer on a board with 6 or more layers, the escape routing from inner ball rows often cannot reach available routing layers using only through-hole vias because those vias consume space on every layer they pass through. Blind vias from Layer 1 to Layer 2 or Layer 3 allow signals to drop down to routing layers without blocking channels on layers 4 through the bottom. This is particularly important for FPGAs, large processors, and memory controllers where pin counts exceed 500 and multiple inner ball rows must be routed.

However, not every design with a BGA needs blind vias. If the BGA pitch is 1.0mm or coarser, if the pin count is under 400, or if the board has enough layers to provide adequate routing channels even with through-hole vias occupying space on all layers, then blind vias add cost without functional benefit. This is the most common over-engineering scenario we encounter: designers specify blind vias because the design has a BGA, when the BGA pitch and pin count would route cleanly with through-hole vias on a well-planned stackup.

Buried Vias: Inner-Layer-Only Connections for Maximum Routing Density

Buried vias connect inner layers exclusively and never reach either outer surface of the finished board. After final lamination, they are completely invisible from the outside, detectable only through electrical testing or cross-sectional analysis. Their primary value is freeing both outer surfaces from any via presence, preserving maximum component placement area and outer-layer routing density.

Manufacturing buried vias requires drilling and plating operations on inner cores before those cores are laminated into the final stackup. The sequence is: fabricate individual inner-layer cores (image, etch, inspect), drill through-holes in specific cores, plate those holes, then stack and laminate all cores together with prepreg layers. The former through-holes in the inner cores become buried vias in the finished board because additional layers now exist above and below them.

This process adds significant cost. Buried vias increase fabrication pricing by 40-60% over through-hole-only designs, and when combined with blind vias in the same board (which is common in complex HDI builds), the total premium can exceed 80%. The cost drivers are multiple: each inner core that contains buried vias requires its own drilling, plating, and inspection cycle before lamination; registration between separately-processed cores must be maintained through the lamination step; and yield loss from core-to-core misalignment is higher than standard processing.

Lead time impact is proportionally severe. Buried vias add 5-7 working days because the inner cores cannot enter lamination until their drilling, plating, and inspection are complete. For complex builds with both blind and buried structures, total fabrication lead time can reach 15-20 working days compared to 5-7 days for a through-hole-only board of equivalent layer count.

From a DFM perspective, the most common failure mode with buried vias is registration error between the buried via holes and the pads on adjacent layers that were separately imaged and etched. During lamination, thermal expansion can shift layers by 1-2 mil relative to each other, and this shift directly reduces the effective annular ring of the buried via connection. Designers should specify minimum annular ring of 4 mil (rather than the standard 3 mil) on buried via pads to accommodate this registration uncertainty.

Our honest recommendation on buried vias: they are the most frequently over-specified via type we encounter. In approximately 60% of designs we receive with buried via specifications, the buried vias could be eliminated by either adding one or two layers (which is often cheaper than the buried via processing premium) or by restructuring the stackup assignment to move the routing connections to layers accessible by through-hole or blind vias. We always check this during DFM review and communicate the option to customers before proceeding with fabrication.

Microvias and HDI: When Standard Drilling Cannot Solve the Problem

Microvias represent a fundamentally different manufacturing technology from mechanically drilled vias. Defined by IPC-T-50 and IPC-2226 as having a maximum diameter of 150 micrometers (6 mil) with an aspect ratio of 1:1 or less and a maximum depth of 0.25mm, microvias are exclusively laser-drilled using either UV (Nd:YAG) or CO2 lasers. They span one dielectric layer only, connecting adjacent layer pairs such as Layer 1 to Layer 2 or Layer 2 to Layer 3.

The laser drilling process ablates the dielectric material (typically resin-coated copper foil or standard prepreg) in a precisely controlled cone shape, stopping at the target copper layer which acts as a drill stop. UV lasers produce smaller, more cylindrical holes suitable for via diameters below 75 micrometers, while CO2 lasers are faster and more cost-effective for diameters between 75 and 150 micrometers. After drilling, a desmear process removes carbonized resin from the hole bottom, followed by electroless copper seeding and electrolytic plating to complete the conductive barrel.

The critical distinction between microvias and standard blind vias is the drilling technology and the resulting dimensional constraints. A standard blind via can be mechanically drilled to 0.2mm (8 mil) minimum diameter and can span multiple layers if drilled carefully. A microvia is limited to 150 micrometers maximum and typically connects only one layer pair, but it can be placed in spaces where a mechanical drill cannot operate and produces far less disruption to surrounding routing channels.

HDI (High Density Interconnect) boards use microvias as their fundamental building block. The IPC-2226 standard classifies HDI builds by the number of microvia layers added to each side of a conventional core. A 1+N+1 build adds one microvia layer per side (one lamination cycle per side), while a 2+N+2 build adds two layers per side (two cycles per side). Each additional HDI level adds a lamination cycle, a laser drilling step, a plating step, and an inspection step, compounding cost and lead time. For a detailed breakdown of HDI cost structures, see our HDI PCB cost analysis comparing 1+N+1 versus 2+N+2 builds.

Cost impact is significant. A 1+N+1 HDI build typically costs 2-3 times the price of an equivalent non-HDI board. A 2+N+2 build runs 3-5 times the base cost. For a reference 8-layer board that costs $15-20 per unit at 100-piece quantity with standard through-hole vias, a comparable HDI design with 1+N+1 structure costs $35-50 per unit, and a 2+N+2 structure reaches $55-80 per unit. These multipliers explain why HDI is reserved for designs where no alternative exists rather than used as a convenient routing solution.

Lead time for HDI boards extends by 7-10 working days over standard processing. A standard 8-layer board ships in 7 days; an equivalent 8-layer HDI (1+N+1, meaning 6-layer core with one buildup layer per side) ships in 14-17 days. More complex structures (2+N+2 or higher) can take 20-25 days.

Stacked Versus Staggered Microvias

When a design requires microvia connections spanning more than one layer pair, microvias must be combined vertically. The two approaches — stacked and staggered — represent a direct trade-off between routing density and long-term reliability.

Stacked microvias are placed directly on top of each other, forming a vertical column. Each level is copper-filled before the next buildup layer is laminated and the next microvia is drilled. This creates the most compact vertical interconnect possible, consuming the minimum possible footprint on each layer. Stacked microvias are essential for fine-pitch BGA fanout where the lateral offset required by staggered approaches would prevent escape routing from inner ball rows.

The reliability concern with stacked microvias is well documented. The interface between stacked levels concentrates thermo-mechanical stress during temperature cycling because copper and dielectric expand at different rates. For an in-depth comparison of stacked versus staggered configurations with thermal cycling data, see our HDI microvia stacked vs staggered reliability guide. Under repeated thermal excursions (as experienced during reflow soldering, thermal testing, and operational cycling), this stress concentration can initiate micro-cracks at the level interfaces. IPC-2226 recommends limiting stacks to two or three levels for this reason. Our production data from interconnect stress testing (IST) shows that two-level stacks achieve 500+ cycles to failure at temperature excursions of 150 degrees Celsius, which satisfies IPC-6012 Class 3 requirements. Three-level stacks show more variability, with 10% of samples failing between 300-400 cycles.

Staggered microvias offset each level laterally by a minimum of 150 micrometers, connecting levels with a short trace on the intermediate layer. This distributes thermal stress across a wider area and eliminates the direct copper-to-copper interface stack that concentrates cracking. In our IST testing, staggered configurations consistently achieve 700+ cycles at the same temperature excursion, representing approximately 40% improvement in thermal cycling reliability over equivalent stacked configurations.

The trade-off is board space. Each stagger offset consumes 150-200 micrometers of routing space on the intermediate layer, and for a three-level transition this can require 400-500 micrometers of lateral space that is not available under dense BGA arrays. For applications in harsh thermal environments — automotive electronics operating from -40 to +125 degrees Celsius, industrial controls, defense electronics — staggered configurations are strongly preferred. For consumer electronics with moderate thermal requirements and severe space constraints, stacked configurations are acceptable within the IPC limits.

Via-in-Pad: Routing Directly Through Component Connections

Via-in-pad (VIP) places a via directly inside a surface-mount component pad rather than routing a short trace from the pad to a via located beside it (the traditional “dog-bone” fanout pattern). This technique becomes necessary when BGA pitch drops below 0.8mm because there is physically no room between adjacent pads for a dog-bone escape trace and its associated via.

The non-negotiable manufacturing requirement for via-in-pad is that the via must be filled and planarized before assembly. An open or partially filled via in a pad creates a capillary channel that wicks molten solder away from the joint during reflow. This solder theft starves the connection, producing either a weak joint with internal voids or a complete open. We have seen this failure mode on customer boards where the design specified via-in-pad but the fabrication note did not explicitly require filling — the assembler reported first-pass yield below 60% due to insufficient solder on affected pads.

The standard solution is VIPPO (Via-In-Pad Plated Over): the via is filled with non-conductive epoxy, the fill is planarized by mechanical abrasion or chemical etch-back to create a flat surface, and then additional copper is plated over the fill to create a smooth, solderable pad surface indistinguishable from a standard SMD pad. Some applications require conductive fill (copper paste or electroplated copper fill) for thermal or electrical conductivity through the via, which costs more but eliminates the thermal resistance of epoxy fill.

Cost impact of via-in-pad filling is moderate compared to the via type itself. The filling and planarization process adds approximately $0.50-1.50 per board at production quantities (500+ pieces) depending on via count and fill type (non-conductive epoxy fill is cheapest, copper fill is most expensive). This is an additive cost on top of whatever the via type itself costs, so a blind via with VIPPO stacks the blind via premium plus the filling premium.

The practical decision point: use via-in-pad when BGA pitch is 0.8mm or finer (our BGA fanout routing strategies guide covers escape routing in detail), when thermal pads under QFN or QFP packages need direct thermal via connections to inner ground planes, or when the routing density around a component is so tight that dog-bone fanout would violate minimum spacing rules. Do not use via-in-pad when pad pitch is generous enough for standard fanout, as the added filling cost and potential yield impact are unnecessary.

Backdrilling: The Signal Integrity Fix That Costs Less Than Blind Vias

Backdrilling (also called controlled-depth back-drilling or stub removal) mechanically removes the unused portion of a through-hole via barrel that extends beyond the last connected signal layer. The result is a through-hole via with its stub eliminated, providing signal integrity performance comparable to a blind via at a fraction of the cost.

The physics driving backdrill adoption is straightforward. A via stub acts as an unterminated transmission line branch that creates a resonant notch in the signal frequency response. The resonant frequency is determined by the stub length: a 40 mil (1mm) stub resonates at approximately 18 GHz (quarter-wavelength in FR-4), but the insertion loss degradation begins well below resonance. For signals at 10 Gbps (which have frequency content extending to 12.5 GHz at the fifth harmonic), even a 60 mil stub produces measurable eye closure. At 25 Gbps, stub lengths above 10 mil become problematic.

The backdrilling process uses a slightly oversized drill bit (typically 2-4 mil larger than the original via hole) to remove the plated copper from the stub portion while leaving a controlled residual stub length. Standard backdrill depth tolerance is plus or minus 4 mil (100 micrometers), meaning a target residual stub of 6 mil will produce actual stubs between 2 and 10 mil. For most 10-25 Gbps applications, this tolerance is acceptable. For 56+ Gbps PAM4 signaling, tighter tolerance of plus or minus 2 mil is achievable with specialized equipment but at higher cost.

The cost comparison is where backdrilling becomes compelling. Adding backdrilling to a standard through-hole via board increases fabrication cost by approximately 5-10%, depending on the number of holes requiring backdrill and the board thickness. Compare this to blind vias at 25-35% premium. For designs where the primary motivation for considering blind vias is signal integrity (eliminating stubs on high-speed nets) rather than routing density, backdrilling achieves the same electrical result at roughly one-third the cost premium.

The decision crossover point is clear: if your design needs partial-depth vias for routing density (BGA escape that cannot route through all layers), blind vias are the correct solution because backdrilling does not help with routing congestion. If your design has adequate routing density with through-hole vias but needs stub reduction for high-speed signal integrity, backdrilling is almost always the more cost-effective approach.

Lead time impact of backdrilling is minimal — typically 1-2 days additional compared to 3-5 days for blind vias. The backdrill operation occurs after standard through-hole drilling and plating, adding one mechanical step rather than requiring sequential lamination restructuring.

Real Production Cost Comparison: What Each Via Type Actually Adds

The following cost data comes from our production quoting system, based on a reference design of an 8-layer FR-4 board, 100x100mm, 1.6mm thick, 1oz copper, ENIG finish, with standard specifications. Prices represent 100-unit production quantity.

The baseline through-hole-only build costs approximately $16-20 per unit depending on hole count and trace complexity. All percentages below reference this baseline.

Through-hole vias only represent the baseline with zero premium, standard lead time of 5-7 working days, and no additional processing requirements. This is the default for all boards unless a specific engineering requirement drives a different choice.

Adding blind vias to the design creates a 25-35% cost premium ($20-27 per unit) and extends lead time by 3-5 days to a total of 8-12 days. This requires sequential lamination, additional drilling operations, and extra inspection. The premium increases toward 35% when blind vias span more than one layer pair (requiring deeper controlled-depth drilling or multiple sequential laminations).

Adding buried vias results in a 40-60% cost premium ($22-32 per unit) with lead time extension of 5-7 days to a total of 10-14 days. Multiple inner core processing cycles before final lamination drive this cost. When combined with blind vias in the same board, the total premium reaches 60-80%.

HDI microvia builds (1+N+1 structure) multiply the base cost by 2-3 times ($32-60 per unit) and add 7-10 days lead time for a total of 12-17 days. More complex HDI structures (2+N+2) multiply cost by 3-5 times and can take 20-25 days. These costs reflect laser drilling equipment time, multiple lamination cycles, and the lower panel yield inherent to HDI processing.

Via-in-pad filling adds $0.50-1.50 per board on top of whatever via type is used. Non-conductive epoxy fill is at the low end; conductive copper fill is at the high end. This is a per-board adder rather than a percentage because the filling process cost scales with board area and via count rather than with overall board complexity.

Backdrilling adds 5-10% to the base cost ($17-22 per unit) with minimal lead time impact of 1-2 additional days. This makes it the most cost-effective signal integrity improvement available when stub elimination is the primary goal.

One critical insight that many engineers miss: upgrading to a more complex via type sometimes enables reducing the layer count, which can result in a net cost reduction. A 12-layer board with through-hole vias that switches to a 10-layer design with blind vias may actually cost less because two fewer layers of copper, prepreg, lamination, and imaging offset the blind via premium. We encounter this optimization opportunity on approximately 15% of designs where blind or buried vias are justified.

Decision Framework: Choosing Via Types Without Over-Engineering

Rather than abstract guidelines, here are the specific thresholds that determine which via type a design requires. These thresholds come from analyzing thousands of designs through our facility and correlating via type choices with actual fabrication outcomes.

Start with through-hole vias as the default for every design. Only add complexity when one of the following specific conditions exists and cannot be resolved by stackup restructuring.

For BGA pitch of 1.0mm or coarser with fewer than 400 pins on boards with 8 or fewer layers, through-hole vias are almost always sufficient. The escape routing works because the via pitch between BGA pads leaves adequate channels on inner layers.

For BGA pitch of 0.8mm with 400-800 pins on boards with 8-12 layers, blind vias become justified to enable inner-row escape routing. The first two inner ball rows can typically escape with through-hole vias using dog-bone fanout, but rows 3 and beyond need layer transitions that do not block channels on every layer.

For BGA pitch of 0.65mm or finer, or for any BGA with more than 800 pins in a space-constrained design, microvias (HDI) become necessary. No amount of stackup optimization substitutes for the small footprint of a laser-drilled microvia when pad-to-pad spacing is less than 250 micrometers.

For high-speed signals above 10 Gbps on boards where through-hole via routing density is adequate, evaluate backdrilling before blind vias. If signal integrity simulation shows unacceptable stub resonance, add backdrilling at 5-10% cost rather than restructuring the entire fabrication process for blind vias at 25-35%.

For boards with 10 or more layers and extreme inner-layer routing density (where signals must connect between layers that are not accessible from either surface), buried vias become the only option. Verify first that adding 1-2 layers to the standard stackup would not resolve the routing congestion at lower total cost.

For thermal pad applications under QFN, QFP, or power packages, via-in-pad with thermal vias provides the lowest thermal resistance from pad to internal ground plane. Specify epoxy fill for signal vias and consider copper fill for thermal vias where heat dissipation is critical.

DFM Rules by Via Type: What Your Fabricator Needs You to Get Right

Each via type introduces specific DFM requirements beyond the general PCB design rules. Violating these rules does not always cause a Gerber rejection — sometimes the board simply fails in the field after thermal cycling or develops yield problems during assembly. These are the rules we check on every incoming design.

For through-hole vias, the critical DFM parameters are aspect ratio (board thickness divided by drill diameter must stay below 10:1 for standard processing, below 8:1 for high-reliability Class 3), minimum annular ring (3.5 mil outer layer, 3 mil inner layer after registration tolerance is applied), and minimum via-to-via spacing (center-to-center spacing must accommodate anti-pads without violating plane clearance). The most common DFM rejection reason for through-hole vias is insufficient annular ring at high-aspect-ratio holes where the drill tolerances consume most of the available land.

For blind vias, add controlled-depth drill tolerance (plus or minus 2 mil for mechanical drilling, plus or minus 0.5 mil for laser) to your consideration. The via must fully penetrate the target copper layer without damaging the next layer below it. Specify the target layer clearly in your fabrication notes — ambiguous blind via depth callouts are a top-five reason for fabrication queries that delay your order by 1-2 days while engineering seeks clarification.

For buried vias, registration between sub-assemblies during final lamination is the dominant DFM concern. Use 4 mil minimum annular ring instead of the standard 3 mil to accommodate layer-to-layer shift. Also consider that buried via processing occurs on individual cores before lamination — if your buried vias require high-aspect-ratio drilling on thin cores, the plating uniformity challenge may be different from through-hole plating on the full-thickness board.

For microvias, the IPC-2226 aspect ratio limit of 1:1 should be treated as a maximum rather than a target. Design to 0.75:1 whenever possible because this improves plating coverage at the via bottom (the desmear and seeding step at the bottom of a cone-shaped laser hole is the most critical reliability point). Capture pad diameter should be at least 100 micrometers larger than the laser hole diameter, and target pad diameter at least 75 micrometers larger.

For via-in-pad, specify the fill material (non-conductive epoxy, conductive paste, or electroplated copper), the cap method (copper plating over fill), and the planarity requirement (typically plus or minus 0.5 mil from surrounding copper surface). Missing any of these specifications in your fabrication notes forces the fabricator to assume a default process that may not match your assembly requirements.

Common Over-Engineering Scenarios We See Weekly

From reviewing hundreds of designs per month, specific over-engineering patterns recur frequently enough to document as cautionary examples.

The first and most common is specifying blind vias on a 6-layer board with only 0.8mm pitch BGA packages that have fewer than 300 pins. At this pin count and pitch, the outer two rows of BGA balls escape using dog-bone fanout with through-hole vias, and the few remaining inner-row signals can route on internal layers without requiring partial-depth vias. Adding blind vias to this design adds 25-35% to board cost with no routing benefit. The solution: verify escape routing feasibility on the standard stackup before specifying blind vias.

The second pattern is specifying buried vias on boards where one or two additional layers would solve the routing congestion at lower total cost. A 10-layer board with buried vias typically costs 40-60% more than the baseline. A 12-layer board with through-hole vias only costs approximately 30-40% more than the 10-layer baseline because it adds two simple copper and prepreg layers without changing the fabrication process complexity (see our 10-layer and 12-layer PCB stackup guides for cost comparison data). The 12-layer through-hole-only board is often cheaper AND faster to fabricate than the 10-layer buried via board.

The third pattern is specifying HDI microvia builds when the design has only one or two fine-pitch BGAs surrounded by standard 0.8-1.0mm pitch components. In many of these cases, the fine-pitch area can be routed with blind vias instead of microvias, using controlled-depth mechanical drilling at 0.2mm (8 mil) diameter. This substitution drops the cost multiplier from 2-3x (HDI) to 1.25-1.35x (blind via), which on a $20 baseline board represents a saving of $15-33 per unit.

The fourth pattern is specifying via-in-pad with copper fill for all vias in a BGA area when only the thermal pad vias actually need conductive fill. Signal vias under BGA balls need epoxy fill (cheaper, sufficient for electrical connection through the barrel), while only the central thermal pad benefits from copper fill’s thermal conductivity. Separating these specifications in the fabrication notes can save $0.30-0.80 per board.

Via Reliability: What Thermal Cycling Data Actually Shows

Via reliability under thermal stress is the ultimate test of manufacturing quality, and different via types show distinctly different failure modes and lifetimes in accelerated testing. Our quality lab performs interconnect stress testing (IST) and thermal cycling per IPC-TM-650 on production samples from every new via configuration we process.

Through-hole vias with proper plating thickness (25 micrometers minimum barrel) consistently achieve 1000+ thermal cycles at delta-T of 150 degrees Celsius before resistance increase indicates incipient failure. The failure mode is barrel cracking at the point of maximum mechanical stress, typically where the barrel transitions from the copper land to unsupported dielectric. Aspect ratios above 8:1 reduce cycle count by approximately 20-30% because the longer barrel has more cumulative thermal expansion mismatch.

Blind vias behave similarly to through-hole vias for reliability because the barrel structure and plating requirements are comparable. The additional failure mode specific to blind vias is separation at the base of the hole where the plated barrel meets the target pad on the landing layer. This interface is mechanically weaker than a barrel-to-pad connection in a through-hole via because the blind via base cannot be mechanically supported from both sides. Proper desmear and adequate plating thickness at the hole bottom mitigate this risk.

Microvias (single-level) show excellent reliability when filled with copper — typically exceeding 1000 cycles without measurable degradation. Their short length and small diameter minimize the thermal expansion mismatch that drives barrel cracking in longer vias. Stacked microvias are the reliability concern point, as described in the stacked versus staggered section above, where level interfaces concentrate stress.

The practical takeaway for designers: specify via plating thickness explicitly in your fabrication notes rather than relying on default processing. Minimum 20 micrometers average with 18 micrometers minimum at any point (IPC Class 2) is adequate for commercial applications. For automotive, medical, or aerospace applications where thermal cycling is severe, specify 25 micrometers minimum (IPC Class 3) and request IST coupon testing with the production lot.

What to Include in Your Fabrication Package for Via Structures

When submitting a design with advanced via structures for quotation and fabrication, the clarity of your documentation directly affects quote accuracy, query turnaround time, and first-article success rate. Missing or ambiguous via specifications are the number one cause of fabrication engineering queries in our facility, each of which adds 1-2 days to order processing.

Your fabrication notes should specify, at minimum, the following via-related information. For blind vias: specify the span (which outer layer to which inner layer), drilling method if you have a preference (laser versus mechanical), and whether the blind via requires filling. For buried vias: specify which inner layers are connected and whether any buried vias also require filling (uncommon but sometimes needed for sequential lamination builds). For microvias: specify the HDI build structure (1+N+1, 2+N+2, etc.), whether microvias are stacked or staggered, and whether copper fill is required for stacked structures. For via-in-pad: specify fill material, planarization requirement, and which specific vias require this treatment (often a subset of all vias on the board).

Additionally, include a drill table in your Gerber package that clearly distinguishes via types by hole size and type code. Many CAD tools can output separate drill files for different via types (standard, blind, buried, microvia), which eliminates ambiguity in the fabrication process. If your CAD tool combines all holes into one drill file, add clear fabrication notes identifying which hole sizes are which via types and which layers they connect.

Reviewed by AtlasPCB Engineering Team

This article is based on production data from our fabrication facility processing thousands of via structures monthly. Cost figures represent actual production quoting from our facility as of 2026 and may vary based on board specifications, quantity, and material requirements. For specific pricing on your design, submit your Gerber files for an individual quote.