High Speed PCB Manufacturing
High-Speed PCB Manufacturer Signal Integrity to 112G PAM4
PCB fabrication engineered for 56G and 112G SerDes channels. Ultra-low-loss materials, precision impedance control, optimized via structures, and verified insertion loss on every production lot.
Capabilities
High Speed PCB Capabilities
Everything your 56G/112G channel needs from the board.
Ultra-Low-Loss Materials
Full Megtron ladder (6 / 7 / 8 / 9) plus Astra MT77, IT-968SE, S7439. Hybrid stackups with FR-4 on non-critical layers to reduce cost.
Back-Drilling
CNC-controlled stub removal on through-hole vias. Depth accuracy ±0.1mm. Cross-section verified on first article.
Impedance Control
Single-ended and differential ±8% tolerance standard. Enhanced ±5% available. TDR tested 100%.
Low-Roughness Copper
HVLP and HVLP2 foils (Rz under 2-3um) for inner and outer layers. Reduces conductor loss 15-25% vs standard ED copper.
High Layer Count
Up to 40 layers with sequential lamination. Tight registration for pad-on-via alignment across 20+ layer transitions.
Insertion Loss Testing
VNA-based insertion loss measurement on test coupons. Verifies that production boards meet your loss budget per inch.
Anti-Pad Optimization
Non-functional pad removal (NPTH) and optimized anti-pad geometry to minimize via-to-trace coupling and return loss.
Glass Weave Mitigation
Spread-glass prepreg and trace rotation options to reduce fiber-weave skew on differential pairs above 25 Gbps.
Mixed Dielectric Stackup
Combine ultra-low-loss laminates on signal layers with standard FR-4 on power/ground. Saves 30-50% vs all-low-loss.
Signal Integrity
Why High Speed PCB Is Different
At 28 Gbps NRZ and above, the PCB is no longer just a mechanical carrier for components. It becomes the dominant contributor to channel loss. A standard FR-4 board running at 56 Gbps PAM4 will lose 1.0-1.5 dB/inch on inner-layer striplines, which exhausts most transceiver equalization budgets before the signal reaches the receiver. High speed PCB manufacturing treats the board as a transmission line system from the first day of stackup planning through final electrical verification.
The challenge is threefold. First, dielectric loss in the substrate material dominates above 10 GHz, so the laminate selection determines whether your channel will close. Second, copper roughness on the trace surface adds 0.2-0.5 dB/inch at 28 GHz depending on foil type, and this roughness is invisible in your EDA tool. Third, via stubs, even 5-mil stubs left by incomplete back-drilling, create resonances that destroy signal integrity at specific frequencies. Managing all three variables simultaneously, in production at volume, is what separates a high speed PCB manufacturer from a standard one.
Dielectric Loss Control
We build the full Panasonic Megtron ladder — Megtron 6 (Df 0.004), Megtron 7 (Df 0.002), Megtron 8 (Df 0.0008), and Megtron 9 (Df 0.0005) — alongside Isola Astra MT77 (Df 0.0017), ITEQ IT-968SE (Df 0.0015), and Shengyi S7439 (Df 0.0013). Material selection is matched to your data rate and channel length. At 112G PAM4, one step on that ladder is the difference between a channel that closes and one that fails.
Copper Roughness Management
Standard electrodeposited copper (ED foil) has Rz roughness of 5-8um. At 28 GHz, that adds 0.3-0.5 dB/inch to your loss budget. We offer HVLP (Rz under 3um) and HVLP2 (Rz under 2um) foils as standard options for high speed stackups. The roughness is specified on your stackup drawing and verified by cross-section.
Via Stub Elimination
Via stubs above 10 mil create quarter-wave resonances below 20 GHz that appear as deep notches in your S21 plot. We back-drill every high speed via to within 0.1mm of the target layer, verified by cross-section on first article. For designs above 56G, we recommend blind/buried via structures that eliminate stubs entirely.
Insertion Loss Verification
VNA-based insertion loss measurement on test coupons matched to your actual trace geometry verifies that production boards meet your loss budget per inch — catching material lot-to-lot variation before it reaches your assembly line.
High-Speed Boards We Build
Controlled-impedance multilayers, in the wild
Manufacturing Process
From Stackup Review to Verified Loss
Every high speed PCB order begins with a stackup review and ends with electrical verification. Here is what happens on our floor — and why each control matters for your loss budget.
Stackup & Channel Review
Every order begins with a stackup review — we model your target impedance and estimate insertion loss per inch from your chosen material and copper roughness, confirming fabrication can deliver what your channel simulation predicts.
Material Selection
The laminate is matched to your data rate and channel length — Megtron 6 for 56G, Megtron 7 for 112G, Megtron 8/9 for 224G and CPO, or the Astra MT77 / IT-968SE / S7439 equivalents. One grade on the Megtron ladder decides whether the channel closes.
Impedance-Controlled Fabrication
Single-ended and differential lines built to ±8% standard (±5% enhanced) and TDR tested 100%. Etch factor and dielectric height are held tight so measured impedance matches the stackup model.
Sequential Lamination
Up to 40 layers with sequential lamination, holding registration tight enough for pad-on-via alignment across 20+ layer transitions on low-loss laminate.
Back-Drilling with X-ray Depth Control
Back-drill depth is set by X-ray measurement of inner-layer position on each panel — not a fixed depth from the board surface — compensating for lamination thickness variation and holding stub length below 5 mil at ±0.1mm.
Pre-Production Test Vehicle
For 112G PAM4 designs we run pre-production test vehicles to verify insertion loss before committing your full lot, catching material lot-to-lot variation, etch factor drift, and plating thickness effects before assembly.
Insertion Loss Verification
VNA-based S-parameter measurement on coupons matched to your trace geometry reports insertion loss (S21) and return loss (S11) from DC to your Nyquist frequency, per-lot or per-panel.
Finish & Final Electrical Test
Solder mask, surface finish, and full electrical test complete the board, with first-article cross-sections confirming back-drill depth and impedance on every new design.
Materials & Stackup
Matched to your data rate and channel length
Choosing the right laminate is the single decision that determines whether your channel closes. We build across the whole Panasonic Megtron ladder — Megtron 6 for 56G, Megtron 7 for 112G, Megtron 8 for 224G, and Megtron 9 for co-packaged optics — plus Isola, ITEQ, and Shengyi equivalents where availability or cost favours them, and standard FR-4 for short-reach DDR4 and USB 2.0.
Hybrid stackups place ultra-low-loss material only on the signal layers while keeping standard FR-4 on power and ground, cutting 30-50% off an all-low-loss construction with negligible impact on channel performance. The same trick works inside the Megtron family: Megtron 8 on the two or four 224G pairs, Megtron 6 everywhere else.
| Material | Dk | Df | Max Data Rate | Best For |
|---|---|---|---|---|
| Megtron 9 | 2.9 | 0.0005 | 224G+ PAM4 | Co-packaged optics, 448G prototyping |
| Megtron 8 (R-5785N) | 3.0 | 0.0008 | 224G PAM4 | 51.2T+ switch fabric, AI/HPC backplanes |
| Megtron 7 (R-5785) | 3.3 | 0.002 | 112G PAM4 | 800G switches, AI accelerators |
| Megtron 6 (R-5775) | 3.4 | 0.004 | 56G PAM4 | PCIe Gen5, 400GbE |
| ITEQ IT-968SE | 3.16 | 0.0015 | 112G PAM4 | AI servers, HPC |
| Isola Astra MT77 | 3.00 | 0.0017 | 112G PAM4 | Data center, 800GbE |
| Shengyi S7439 | 3.0 | 0.0013 | 112G PAM4 | Cost-optimized 112G |
| Shengyi S7040G | 3.72 | 0.0089 | 28G NRZ | PCIe Gen4, 25GbE |
| Isola 370HR | 4.04 | 0.021 | 10G NRZ | DDR4, USB 3.2, GbE |
| Standard FR-4 | 4.2-4.7 | 0.02 | 5-10G | DDR4 short reach, USB 2.0 |
Not sure which material your channel budget requires? Send us your data rate, channel length, and equalization capability. Our SI engineers will model the channel and recommend the most cost-effective laminate. See our full material library for detailed datasheets.
Panasonic Megtron
Megtron 6, 7, 8 and 9 — which grade your channel actually needs
Megtron is the reference family for high-speed digital PCBs, and most of the boards on this page are built on it. The grades are not interchangeable: each step down the Df ladder roughly halves dielectric loss, and each step up the ladder costs more and takes longer to source. Choosing one grade too low means a channel that fails at temperature; one grade too high means paying two to three times the laminate cost for margin you will never use.
The rule of thumb we use in stackup review: multiply your per-inch insertion loss by the longest channel on the board, add 2 dB for connectors and vias, and compare against the transceiver's stated budget. If you are within 3 dB, move up a grade — production variation in resin content, etch factor, and copper roughness will eat that margin.
All four grades run on the same line here, with HVLP2 foil, back-drilling, and spread-glass prepreg available on each. Megtron 8 and 9 are allocation materials, so send your stackup early — we confirm mill availability before we confirm a date.
Megtron 6
R-5775 28–56G PAM4Df 0.004 @ 10 GHz
The volume workhorse. Processes identically to high-Tg FR-4 — same drill, plating, and lamination cycle — so there is no qualification penalty. Right for PCIe Gen4/Gen5, 100GbE (4×25G), and 56G channels under 6–8 inches.
Megtron 7
R-5785 112G PAM4Df 0.002 @ 28 GHz
Half the loss of Megtron 6, from AGC T-Glass reinforcement plus a low-Df resin system. Buys roughly 3–4 dB of extra link budget over a 10-inch channel. T-Glass supply is the constraint, so we confirm availability before we confirm your order.
Megtron 8
R-5785N 224G PAM4Df 0.0008 @ 28 GHz
About 40% lower loss than Megtron 7, validated for 224G PAM4 channels out to 12 inches. This is the grade for 51.2T+ switch fabrics and AI training-cluster interconnect. Available on allocation for qualified designs.
Megtron 9
224G+ / CPODf 0.0005 @ 28 GHz
Panasonic's flagship. Dk 2.9 and the lowest Df in the family, for co-packaged-optics host boards and 448G prototyping — where the electrical-to-optical transition leaves no loss margin anywhere else in the channel.
Grades below Megtron 6 (Shengyi S7040G, Isola 370HR, standard FR-4) are listed in the table above — they are the right call for 28G NRZ and slower, where paying for Megtron buys nothing.
Design Guidelines
DFM for High-Speed Success
A handful of design choices decide whether your channel closes in production. These are the DFM recommendations our SI engineers apply to every high speed review.
Via Design
For signals above 25 Gbps, avoid through-hole vias routed on inner layers unless back-drilling is specified. Preferred: blind/buried vias or through-hole with back-drill. Anti-pad diameter should be 20 mil larger than drill diameter minimum to control return loss. Remove non-functional pads on all non-connected layers.
Trace Geometry
Target 4-5 mil trace width for 100-ohm differential stripline on Megtron 6 (Dk 3.4, 4 mil dielectric). Below 3.5 mil, etch factor variability starts to dominate impedance tolerance. Where possible, widen traces and increase dielectric height rather than shrink geometry. This reduces both loss and manufacturing risk.
Reference Plane Integrity
Every high speed trace must have an uninterrupted reference plane directly above or below. If the signal transitions layers (via), the return current must also transition via a nearby ground via within 20 mil. Split planes under differential pairs will cause common-mode conversion and EMI.
Material Specification
Specify the laminate system by name and grade, not by generic Dk/Df values. "Dk 3.4, Df 0.004" matches five different products with different mechanical and thermal properties. Call out the exact material and part number ("Panasonic Megtron 6 R-5775", "Megtron 8 R-5785N") and the foil type (HVLP or HVLP2) explicitly in your fab notes. On mixed-dielectric builds, name the material per layer pair — otherwise the stackup gets built to the cheapest reading of your note.
Applications
High-Speed Systems We Build For
We fabricate boards for these high speed systems daily.
AI / HPC Servers
GPU interconnect backplanes at 112G PAM4, NVLink and PCIe Gen5/6 switch boards, AI training cluster fabric. Typically 20-32 layers on Megtron 7 (or Megtron 8 for 224G links) with HVLP2 copper.
Data Center Networking
400G and 800G Ethernet switch line cards. Retimer boards, optical module host boards, and orthogonal midplane connectors. Channel loss budgets of 25-30 dB at Nyquist frequency. 51.2T+ fabrics move to Megtron 8.
5G Infrastructure
Baseband processing cards with 25G CPRI/eCPRI links. Fronthaul and midhaul interface boards. Mixed-material stackups combining Megtron 6 signal layers with standard power distribution.
High-Speed Test Equipment
Oscilloscope front-end boards, BERT interposer cards, and channel emulation boards requiring insertion loss repeatability across production lots to within 0.1 dB/inch.
Automotive Ethernet
In-vehicle 10GBASE-T1 and 25GBASE-T1 domain controllers. Zonal architecture backbone boards requiring low-loss with automotive-grade laminate (Tg 170+, CAF resistant).
Memory Modules
DDR5 RDIMM and LRDIMM substrates, CXL memory expander boards, and HBM interposers. Tight impedance matching (±5%) and length matching within 2 mil for data bus groups.
The Difference
Why High-Speed at AtlasPCB
The hard part of high speed isn't whether the board can be made — it's whether the finished channel matches your simulation. Our process is built around proving it does.
SI Engineering Review
Our SI engineers model your channel, estimate per-inch loss, and recommend material or geometry changes before you commit — free for production orders.
Verified Loss Budget
VNA insertion-loss testing on coupons matched to your trace geometry confirms production boards meet the loss budget your simulation predicted.
Back-Drill Precision
X-ray inner-layer measurement per panel holds stub length below 5 mil at ±0.1mm, killing the resonances that notch your S21 plot.
Full Megtron Ladder
Megtron 6, 7, 8, and 9 all run on our line — plus Astra MT77, IT-968SE, and S7439 — with hybrid stackups to place the expensive grade only where the channel needs it.
FAQ
High Speed PCB Questions
112 Gbps PAM4 per lane (800G Ethernet, PCIe Gen6) is routine volume work for us on Megtron 7 class laminate. 224 Gbps PAM4 is supported on Megtron 8 and Megtron 9 for qualified designs, subject to material allocation. The constraint at either rate is material selection and via structure, not our process capability — we will help you pick the combination that matches your target.
Megtron 6 (Df 0.004 at 10GHz) handles 28G NRZ and 56G PAM4 channels up to about 6-8 inches. For 112G PAM4, or 56G channels longer than 8 inches, move to Megtron 7 (Df 0.002 at 28GHz) or the Astra MT77 / IT-968SE equivalents. We can model your specific channel to confirm before you commit to a laminate.
Megtron 6 (Df 0.004) for PCIe Gen4/Gen5, 100GbE, and 56G under 8 inches. Megtron 7 (Df 0.002) for 112G PAM4 and 800G switching. Megtron 8 / R-5785N (Df 0.0008) for 224G PAM4 and 51.2T+ switch fabrics out to 12 inches. Megtron 9 (Df 0.0005, Dk 2.9) for co-packaged optics host boards and 448G prototyping. Each step down the ladder roughly halves dielectric loss and raises laminate cost, so we size the grade to your measured loss budget rather than defaulting to the top.
Megtron 8 and Megtron 9 are allocation materials from Panasonic, not shelf stock. We confirm mill availability before we confirm your delivery date; typical material lead time is 2-4 weeks. Megtron 6 and Megtron 7 are held in regular stock, though Megtron 7 depends on AGC T-Glass supply.
Yes, and for 224G designs it is usually the right answer. Megtron 8 goes on the two or four layer pairs carrying the fastest lanes, Megtron 6 or high-Tg FR-4 handles power, ground, and slow-speed routing. The grades share a compatible lamination cycle, so the mixed build does not add process risk — it just needs the stackup drawing to call out material per layer explicitly.
Ultra-low-loss materials (Megtron 6/7 class) typically add 40-80% to board cost versus standard FR-4, depending on layer count and panel size. Megtron 8 and 9 run higher again. Hybrid stackups (low-loss on signal layers, FR-4 on power/ground) reduce the premium to 25-45%, and the same approach works inside the Megtron family.
Yes. We offer VNA-based S-parameter measurement on test coupons matched to your actual trace geometry. The report gives you measured insertion loss (S21) and return loss (S11) from DC to your Nyquist frequency. Available per-lot or per-panel.
Our back-drilling uses X-ray measurement of actual inner layer position on each panel, then drills to within ±0.1mm (4 mil) of the target depth. Stub length is typically held below 5 mil. First article cross-sections confirm depth on every new design.
Yes, and we recommend them. Placing ultra-low-loss material only on signal layers while using standard FR-4 on power and ground layers saves 30-50% versus an all-low-loss construction, with negligible impact on channel performance.
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