Samsung's 2nm GAA Process Enters Risk Production: Implications for PCB Substrate Technology

Samsung’s 2nm GAA Process Enters Risk Production: Implications for PCB Substrate Technology

Samsung Foundry has officially entered risk production on its SF2 process node — the company’s first 2nm-class technology built on Gate-All-Around (GAA) nanosheet transistors. This milestone, confirmed through Samsung’s Q1 2026 earnings disclosures and corroborated by supply chain reports, marks a fundamental shift in semiconductor architecture that will ripple through every layer of the electronics stack, from IC packaging to printed circuit board design.

For PCB engineers and fabricators, the implications are neither theoretical nor distant. The transistor density improvements enabled by GAA architecture directly drive higher chip I/O counts, which in turn demand finer-pitch packaging, more advanced substrate technology, and tighter PCB design rules. Understanding these cascading effects is essential for anyone designing boards that will host next-generation silicon.

What GAA Means at the Transistor Level

Gate-All-Around represents the most significant change in transistor geometry since Intel introduced FinFET at the 22nm node in 2012. Where FinFET wraps the gate around three sides of a vertical fin, GAA wraps the gate around the entire channel on all four sides using stacked horizontal nanosheets.

Samsung’s SF2 process uses three stacked nanosheets per transistor, each approximately 5–6nm wide. This geometry provides:

• ~1.4× logic density compared to Samsung’s 3nm SF3E process
• 25–30% power reduction at equivalent performance
• 12–15% performance improvement at equivalent power
• Approximately 50 billion transistors on a large die (~300mm²)

The density figure is what matters most for PCB and packaging engineers. More transistors per unit area means more functionality per chip, which means more signals entering and leaving the die.

The I/O Explosion: From Die to Package to Board

Every generation of transistor scaling has followed a consistent pattern: more transistors enable more on-die functionality, which demands more I/O connections to the outside world. Samsung’s 2nm process amplifies this trend significantly.

Consider the progression for a high-performance compute (HPC) die:

These numbers have direct consequences for everything downstream of the die:

IC substrate requirements. With bump pitches below 0.30mm, IC substrates must support line/space geometries of <25μm/<25μm and dielectric thicknesses under 20μm. ABF (Ajinomoto Build-up Film) substrates with semi-additive processing (SAP) become mandatory rather than optional. The substrate layer count for HPC packages is expected to reach 16–20 layers, up from 12–14 for current-generation designs.

Package-to-board interface. The BGA ball array connecting the package to the PCB is also getting denser. For flagship applications, ball pitches are moving to 0.40–0.50mm at the board level (after fan-out through the substrate), down from 0.65–0.80mm in earlier generations. This is still manageable with advanced HDI PCB technology, but it pushes designs firmly into via-in-pad territory and demands tighter registration tolerances.

PCB Design Implications: Five Critical Areas

1. Finer Line/Space and HDI Stackups

To escape route from a <0.50mm pitch BGA, PCB designers need trace widths and spaces that conventional subtractive etching struggles to achieve reliably. The math is straightforward: with a 0.40mm pitch BGA, the available channel width between pads for escape routing is approximately 150–200μm, requiring trace/space of 50μm/50μm (2mil/2mil) or finer.

This pushes designers toward:

• Any-layer HDI construction with stacked microvias
• Modified Semi-Additive Process (mSAP) or semi-additive processing for <50μm features
• Higher layer counts (12–16 layers for mobile; 20+ for HPC)

For a comprehensive approach to HDI stackup design, engineers should reference advanced HDI stackup methodologies and consider BGA escape routing strategies that account for these finer geometries.

2. Power Delivery Network Challenges

The 2nm GAA transistor is more power-efficient per operation than its FinFET predecessors, but the sheer density increase means total die power for HPC applications can exceed 300W. At supply voltages of 0.65–0.75V, this translates to currents exceeding 400A — a staggering figure that must be delivered through the PCB and package with minimal voltage drop.

PCB-level implications include:

• Dense decoupling capacitor placement. Capacitors must sit within 1–2mm of BGA pads, requiring careful pad design for fine-pitch SMT and sophisticated power island partitioning
• Heavy copper power planes. Inner-layer copper weights of 2–4oz are increasingly common, with localized coin insertion for extreme current requirements
• Via-based current distribution. Dense arrays of power/ground vias connecting decoupling caps to internal planes become critical — the via resistance itself becomes a meaningful contributor to PDN impedance
• PDN impedance targets below 1mΩ across a frequency range from DC to 1 GHz, requiring careful analysis with tools described in our power integrity and decoupling guide

3. Signal Integrity at Faster Edge Rates

GAA transistors switch faster than FinFETs at equivalent power levels. For high-speed I/O circuits built on 2nm, edge rates are expected to drop below 10ps (10–90% rise/fall time) for next-generation SerDes running at 224 Gbps PAM4.

At these speeds, the PCB is no longer a passive interconnect — it’s an integral part of the RF channel. Designers must account for:

• Dielectric loss dominance. Skin effect losses matter, but Df (dissipation factor) of the laminate becomes the primary loss contributor above 30 GHz. Standard FR-4 (Df ≈ 0.02) is wholly inadequate; ultra-low-loss materials with Df <0.003 are required
• Surface roughness effects. Copper roughness that was negligible at 10 Gbps becomes a significant loss contributor at 112+ Gbps. VLP (Very Low Profile) or HVLP (Hyper Very Low Profile) copper foils are mandatory
• Via stub elimination. Back-drilling or blind via construction is essential for any signal path above 56 Gbps. Our guide on high-speed PCB design covers these techniques in detail
• Impedance tolerance tightening. ±10% impedance tolerance is insufficient; ±5% or better is required, demanding tighter process controls from fabricators

4. Substrate-Like PCB (SLP) Convergence

Perhaps the most significant long-term trend accelerated by 2nm silicon is the convergence of IC substrate and PCB technology — a category increasingly called Substrate-Like PCB (SLP).

Traditional PCBs and IC substrates have been manufactured using fundamentally different processes and materials. IC substrates use build-up film (ABF) with semi-additive copper patterning to achieve <15μm features, while PCBs use laminated prepreg with subtractive etching for features typically above 50μm.

As chip I/O density increases, the line between these technologies blurs:

• Apple’s iPhone has used SLP mainboards since the iPhone X (2017), with line/space of ~30μm
• Flagship Android devices are adopting SLP for their application processor interposer boards
• AI accelerator modules are exploring SLP for the first layer of fan-out from the chip package

For PCB fabricators, this convergence means investing in SAP/mSAP processing capabilities, laser direct imaging (LDI) with sub-10μm resolution, and ultra-thin core handling equipment. For designers, it means learning IC substrate design conventions — impedance-optimized build-up structures, stacked via reliability rules, and coefficient of thermal expansion (CTE) matching between substrate and PCB.

5. Thermal Management at the Board Level

With die power densities increasing, the thermal management burden doesn’t stop at the heatsink. The PCB itself must contribute to heat spreading, particularly for:

• BGA underfill regions where thermal resistance through the solder joints determines junction temperature
• Power delivery components (voltage regulators, inductors) that generate significant heat
• Thermal via arrays beneath high-power components that conduct heat to internal copper planes or bottom-side heatsinks

Heavy copper construction (3–6oz inner layers), thermal via arrays on 0.5mm pitch, and thermally conductive prepreg materials are all becoming standard requirements for boards hosting 2nm silicon.

Timeline and Industry Readiness

Samsung’s risk production timeline suggests the following progression:

• Q1 2026: Risk production (current status) — limited wafer starts for design validation
• Q3–Q4 2026: Qualification complete, initial volume production
• Q1 2027: Full volume production for lead customers (likely mobile application processors)
• H2 2027: Consumer products (smartphones, tablets) shipping with 2nm chips

TSMC’s competing N2 process follows a similar timeline, roughly 1–2 quarters behind Samsung’s schedule. This means the PCB industry has approximately 12–18 months before boards designed for 2nm silicon enter volume production.

What PCB Designers Should Do Now

The transition to 2nm doesn’t require reinventing the PCB design process, but it does demand proactive preparation:

1. Evaluate your fabricator’s capabilities. Not all PCB manufacturers can produce the fine-feature HDI required for 2nm chip packaging. Confirm that your fabricator supports <50μm line/space, stacked microvia construction, and the ultra-low-loss materials your signal integrity analysis specifies.

2. Update design rules. If your standard design rules assume 0.65mm or 0.8mm pitch BGA, update them to include 0.40–0.50mm pitch rules with appropriate via-in-pad, escape routing, and clearance specifications.

3. Invest in power integrity analysis. The margin for error in PDN design shrinks significantly at 2nm current densities. Full-wave PDN simulation from DC to 1 GHz should become a standard part of the design flow, not an optional check.

4. Consider co-design with packaging. As SLP convergence accelerates, the traditional handoff between IC packaging and PCB design becomes a bottleneck. Co-design workflows where package and board are optimized simultaneously yield better results.

5. Work with your fabricator early. Complex HDI stackups benefit from DFM collaboration before design completion rather than after. Fabricators with 2nm-class board experience can guide stackup optimization, material selection, and yield-critical design rules.

What This Means for Your Next Project

Whether you’re designing next-generation smartphone mainboards, AI accelerator modules, or high-performance compute platforms, Atlas PCB’s engineering team stays ahead of industry developments to deliver optimized solutions. Contact us to discuss how these developments affect your PCB requirements.

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