mSAP vs Subtractive PCB Manufacturing: When Fine-Line Patterning Changes Everything

Reviewed by AtlasPCB Engineering Team

Every PCB in production today exists because copper was either removed from where it should not be, or deposited where it should. That fundamental distinction — subtracting copper versus adding it — defines the two dominant patterning approaches in circuit board manufacturing, and understanding where each one excels determines whether your next design will be manufacturable at acceptable yield or will become an exercise in fighting physics.

For decades, subtractive etching has been the workhorse of the PCB industry. The process is well understood, the equipment is widely available, and the chemistry is mature. A fabricator laminating a standard half-ounce copper foil onto FR-4 and etching away the unwanted copper can produce reliable circuits with trace widths down to about 75 micrometers on outer layers. That capability covers the vast majority of electronic products shipping today, from consumer devices to industrial controls to automotive electronics.

But the trajectory of electronics design is relentless. Package pin counts increase. Signal frequencies climb. Board real estate shrinks. At some point — and that point is arriving faster for many product categories — the conventional subtractive approach simply cannot deliver the trace density a design requires. This is where the modified semi-additive process, universally known as mSAP, enters the picture. Rather than removing copper from a thick foil, mSAP deposits copper onto a thin seed layer, building traces from the bottom up. The physics of this reversal allow dramatically finer features, and the implications for design, material selection, cost, and manufacturing logistics are significant.

At AtlasPCB, we operate both subtractive and mSAP production lines. The perspective we offer here comes not from a textbook comparison, but from the daily reality of processing both types of boards and advising engineering teams on which process their design actually requires.

How Subtractive Etching Defines Most PCBs Made Today

The subtractive process begins with a copper-clad laminate — a sheet of dielectric material (typically FR-4 fiberglass-reinforced epoxy) with copper foil bonded to one or both sides. For a standard multilayer board, inner layer processing starts by laminating photoresist onto the copper surface, exposing it through a photomask or laser direct imager to define the circuit pattern, developing the resist to remove unexposed areas, and then immersing the panel in an etchant solution (typically cupric chloride or ammoniacal copper chloride) that dissolves the exposed copper. After etching, the remaining resist is stripped, leaving copper traces where the resist protected them.

Outer layer processing adds a plating step. After drilling, the panel receives electroless copper deposition to make the hole walls conductive, followed by electroplating to build up copper thickness in the holes and on the surface. Photoresist is applied and patterned, then tin or tin-lead is plated over the exposed copper traces as an etch resist. The photoresist is stripped, the etchant removes the unprotected copper, and finally the tin etch resist is stripped to reveal the finished copper pattern.

This process has been refined over fifty years of industrial practice. Equipment suppliers offer high-speed horizontal conveyorized etching systems that maintain tight control of etchant concentration, temperature, and spray pressure. Modern direct imaging systems eliminate the need for physical photomasks, improving registration and enabling faster design changes. The chemistry is well characterized, the failure modes are understood, and the process window is wide enough to allow high-volume production with consistent quality.

The limitation of subtractive etching is not a matter of process control — it is a matter of physics. Specifically, it is a matter of what fabricators call the etch factor.

Where Subtractive Hits Its Limits — The Etch Factor Problem

Chemical etching is fundamentally isotropic. When etchant contacts a copper surface, it dissolves copper in all directions at approximately equal rates. If you are etching downward through an 18 micrometer copper foil (half-ounce copper), the etchant is simultaneously attacking sideways under the edge of the resist. This lateral etching, called undercut, is unavoidable in any wet chemical process.

The etch factor quantifies this relationship as the ratio of vertical etch depth to lateral undercut on one side. For spray etching with optimized chemistry and nozzle pressure, a typical etch factor falls between 2.5 and 3.5. This means that for every 18 micrometers of copper etched vertically through the foil, the etchant removes roughly 5 to 7 micrometers laterally under the resist on each side, creating a total undercut of 10 to 14 micrometers.

When your target trace width is 150 micrometers (6 mil), an undercut of 12 micrometers represents less than 10 percent of the feature size. The resulting trapezoidal cross-section is well within tolerance, and impedance predictions based on nominal dimensions remain accurate. The process works comfortably.

When your target trace width drops to 75 micrometers (3 mil), that same 12 micrometers of undercut now represents 16 percent of the feature width. The trapezoidal distortion becomes significant. To compensate, the photomask pattern must be widened (a technique called etch compensation), but this compensation consumes the space between adjacent traces, limiting achievable density. The process still works, but the margins are tighter.

At 50 micrometers (2 mil), the undercut is nearly 25 percent of the trace width. The cross-section is distinctly trapezoidal — the base of the trace is substantially wider than the top. Impedance modeling becomes unreliable unless the actual trapezoidal geometry is accounted for. Yield drops because small variations in etch rate or resist adhesion cause traces to open or short. The process can still produce boards, but it requires premium tooling, tighter process controls, and thinner starting copper (typically quarter-ounce or less).

Below 40 micrometers, subtractive etching becomes impractical for production. The undercut is too large relative to the feature size, the compensation margins overlap, and yield falls to levels that make the process economically unviable. This is where the industry reaches for a fundamentally different approach.

How mSAP Works — Building Traces Up Instead of Etching Them Down

The modified semi-additive process inverts the subtractive approach. Instead of starting with a thick copper foil and removing most of it, mSAP starts with an extremely thin copper layer — typically 2 to 5 micrometers deposited by electroless plating or sputtering — and selectively adds copper only where traces are needed.

The process flow for an mSAP outer layer follows this sequence. First, a dielectric layer is applied to the panel surface. In advanced applications, this is typically ABF (Ajinomoto Build-up Film), a thin epoxy film that provides excellent surface smoothness and adhesion. In PCB applications that do not require substrate-level density, a modified prepreg with ultra-low-profile copper foil can serve the same purpose. The dielectric surface is prepared (typically by chemical desmear or plasma treatment) to promote adhesion, and then an ultra-thin copper seed layer is deposited across the entire surface through electroless copper plating.

Photoresist is laminated onto the seed layer and patterned using laser direct imaging to define the circuit traces, but with an important difference from the subtractive approach: in mSAP, the resist is patterned to create open channels where traces should exist, rather than covering where traces should remain. Copper is then electroplated into these open channels, building up the trace thickness to the required dimension (typically 15 to 25 micrometers for signal layers). After plating, the resist is stripped, exposing the thin seed copper in the spaces between traces. A brief differential etch (sometimes called flash etching) removes this thin seed layer without significantly affecting the much thicker plated traces.

The key advantage is immediately apparent. The differential etch only needs to remove 2 to 5 micrometers of seed copper, not 18 micrometers of foil. Even with a modest etch factor, the lateral undercut during this flash etch is measured in single-digit micrometers. The resulting trace has nearly vertical sidewalls, its width at the top is almost identical to its width at the base, and the geometry closely matches the design intent. Impedance calculations based on rectangular trace cross-sections are accurate. Line and space below 30 micrometers becomes routinely achievable, and research facilities have demonstrated features below 10 micrometers using this approach.

SAP vs mSAP vs Subtractive — Understanding the Process Spectrum

The fully additive process, known as SAP (semi-additive process without the “modified” prefix, though terminology varies across the industry), takes the concept even further. In SAP, there is no starting copper foil at all. The seed layer is deposited directly onto the dielectric, patterning and plating proceed as in mSAP, and the seed is removed by differential etching. The distinction is subtle but important: SAP achieves the finest possible features because there is no foil at all to contribute to undercut, but it requires extremely clean and uniform electroless copper deposition and exceptional adhesion to bare dielectric surfaces.

In practice, the terminology often creates confusion. IC substrate fabricators — particularly those producing packages for advanced processors, memory, and AI accelerators — have been running SAP and mSAP processes for over a decade. Their experience represents the leading edge of fine-line patterning. PCB fabricators are increasingly adopting mSAP as a bridge between conventional subtractive processing and full substrate-level capability.

The practical reality is that these three processes form a continuum rather than three discrete categories:

Subtractive processing with standard copper foil covers line and space from about 75 micrometers upward on outer layers and 50 micrometers upward on inner layers. This represents the overwhelming majority of PCB production volume worldwide.

Advanced subtractive processing using ultra-thin copper foils (5 to 9 micrometer “quarter-ounce” or thinner), optimized etch chemistry, and tighter process controls can push into the 40 to 60 micrometer range. This is an important middle ground that we will discuss separately.

mSAP processing with a deposited seed layer covers line and space from about 20 to 50 micrometers, with the sweet spot around 25 to 35 micrometers for volume production.

SAP processing targets features below 20 micrometers, primarily in IC substrate and advanced packaging applications rather than conventional PCBs.

Line and Space Capabilities — The Real Numbers from Production

Theoretical capability and production capability are different things. A laboratory can demonstrate 15 micrometer traces on a test coupon; shipping thousands of production panels with that feature size at acceptable yield is another matter entirely.

From our production experience, these are the practical limits for each process in a volume manufacturing context, defined as achieving first-pass yield above 90 percent on a full production panel:

For standard subtractive outer layers with half-ounce (18 micrometer) copper, the reliable production limit is 75 micrometer line and 75 micrometer space (3/3 mil). At 63 micrometers (2.5 mil), yield begins declining noticeably and close process monitoring is required. Inner layers, which do not undergo the additional etch steps of the pattern-plating process, can reliably achieve 50 micrometer line and space (2/2 mil) with half-ounce copper.

For advanced subtractive processing with quarter-ounce (9 micrometer) or thinner copper, outer layer capability extends to approximately 50 micrometers (2 mil) with careful etch compensation and the acceptance of some trapezoidal distortion. Inner layers can reach 38 to 40 micrometers in favorable conditions. The challenge at this level is not just the etching itself but maintaining uniform copper thickness across the entire panel, since any variation in the starting foil translates directly into etch depth variation.

For mSAP processing with a 2 to 3 micrometer electroless copper seed, production capability comfortably reaches 25 micrometer line and space (approximately 1 mil). With premium tooling and optimized exposure, 20 micrometers is achievable in production, and 15 micrometers has been demonstrated on pilot lines. The limiting factor at these dimensions shifts from etch factor to photoresist resolution, exposure system accuracy, and plating uniformity.

When to Choose mSAP Over Subtractive

The decision to use mSAP should not be driven by a desire for cutting-edge technology. It should be driven by a clear engineering requirement that subtractive processing cannot satisfy. mSAP adds cost, limits your choice of fabrication partners, extends lead times, and introduces material constraints. None of that matters if your routing density demands it, but all of it matters if a conventional process would work.

The primary scenarios where mSAP becomes necessary include high-density BGA breakout routing, where the pad pitch of the component physically cannot be routed with subtractive trace widths. A 0.4 millimeter pitch BGA requires approximately 50 micrometer traces for dog-bone fanout on the top layer. A 0.3 millimeter pitch device pushes into the 30 to 35 micrometer range. At these pitches, there is no subtractive solution that provides acceptable yield.

Layer count reduction is another compelling driver. If a design requires twelve layers with subtractive routing rules but can be collapsed to eight or ten layers with mSAP density, the higher per-layer cost of mSAP may be offset by the elimination of two or four entire layers, the associated reduction in lamination cycles, and the improvement in signal integrity from shorter via stubs. Our HDI PCB cost breakdown explores how layer count reduction translates to real savings.

High-frequency signal integrity applications benefit from the rectangular trace cross-section that mSAP produces. At frequencies above 10 GHz, the trapezoidal profile of a subtractive trace creates measurable impedance variation between the top and bottom of the trace. The near-vertical sidewalls of an mSAP trace produce more predictable impedance and lower loss, which becomes significant in 56G and 112G SerDes channels.

Material Considerations for mSAP Fabrication

The material requirements for mSAP differ fundamentally from subtractive processing, and this difference catches many design engineers by surprise when they first specify an mSAP board.

In subtractive processing, the copper-clad laminate arrives from the material supplier with copper foil already bonded to the dielectric. The fabricator works with this composite material through drilling, imaging, and etching. The bonding between copper and dielectric is mechanical — the copper foil has a rough “tooth” side that physically interlocks with the partially cured resin during lamination.

In mSAP, the copper is deposited after the dielectric surface is prepared, which means the dielectric itself must be compatible with electroless copper deposition and must provide adequate adhesion to a very thin copper layer without the mechanical interlocking that conventional foil bonding provides. This requirement leads to two main material approaches.

The first approach uses ABF (Ajinomoto Build-up Film), which was originally developed for IC substrate manufacturing. ABF is a dry film epoxy that is vacuum-laminated onto the panel, cured, and then chemically or plasma-roughened to create a controlled surface texture for copper adhesion. ABF provides excellent thickness uniformity, fine surface roughness suitable for high-frequency applications, and well-characterized adhesion to electroless copper. However, ABF is more expensive than standard prepreg systems and requires specialized lamination equipment.

The second approach uses modified prepreg systems with ultra-thin copper foils. Some laminate manufacturers offer prepreg products with 2 to 3 micrometer copper foils already bonded to the surface. These materials can be processed through a semi-additive flow where the ultra-thin foil serves as the seed layer, eliminating the need for electroless copper deposition but requiring careful handling of the extremely thin starting copper. This approach represents a lower barrier to entry for fabricators transitioning from subtractive to mSAP capability.

The choice of dielectric material also affects electrical performance. For applications above 10 GHz, the surface roughness of the dielectric becomes a significant contributor to conductor loss. ABF films and low-roughness prepreg systems can achieve surface roughness below 2 micrometers (Rz), compared to 5 to 8 micrometers for standard FR-4 prepregs. This smoother interface reduces the skin-effect losses that dominate at high frequencies.

DFM Guidelines for Designs Targeting mSAP

Designing for mSAP fabrication requires adjustments to your standard design rules, and ignoring these adjustments is one of the fastest ways to encounter problems during manufacturing.

Trace width and spacing minimums are the most obvious change. While mSAP enables 25 micrometer features in production, designing every trace to the process minimum is poor DFM practice. Use mSAP density where you need it — in BGA breakout regions, dense connector fanout, or impedance-critical high-frequency channels — and maintain larger feature sizes elsewhere on the board. This approach maximizes yield by limiting the proportion of the board area that requires tight-tolerance patterning.

Via structures require careful consideration. Microvias used in conjunction with mSAP layers must be designed with appropriate capture and target pads. A 75 micrometer laser-drilled microvia needs a minimum capture pad of approximately 150 micrometers (diameter) on the mSAP layer and a similarly sized target pad on the adjacent layer. These pad sizes are often the true limiting factor for routing density, not the trace width itself.

Copper balance is critical because the differential etch step that removes the seed copper is sensitive to the ratio of plated copper area to seed copper area across the panel. Large copper pours adjacent to dense trace routing can create plating thickness variations that affect the flash etch uniformity. Providing detailed copper balance maps to your fabricator and incorporating copper thieving patterns in open areas helps maintain uniform plating and etching.

Solder mask registration becomes more challenging at mSAP feature sizes. Standard solder mask registration tolerances of plus or minus 50 micrometers may be adequate for conventional designs but can encroach on trace structures when traces are only 25 to 30 micrometers wide. Discuss solder mask dam requirements and registration capabilities with your fabricator before finalizing your design rules.

Cost and Lead Time Implications

The cost premium for mSAP fabrication is real and substantial. For a direct comparison — same layer count, same board size, same material class — mSAP typically adds 40 to 80 percent to the fabrication cost of an equivalent subtractive board. The premium reflects several factors: more expensive dielectric materials (ABF or specialized prepregs), additional process steps (seed layer deposition, differential etching), tighter process controls and cleanroom requirements, and lower throughput due to longer processing times at several stations.

However, the relevant comparison is rarely “same layer count.” The correct comparison is the total cost of the design as built with each process. If mSAP density allows a twelve-layer subtractive design to be implemented as an eight-layer mSAP design, the cost equation changes dramatically. Eliminating four layers removes four lamination cycles, four imaging-and-etching sequences, and four layer-to-layer registration requirements. The thinner board may also reduce drilling time and improve via reliability.

Lead time for mSAP boards is typically one to two weeks longer than equivalent subtractive boards. The additional time reflects the extra process steps, the higher likelihood of engineering review cycles (since mSAP designs are more sensitive to DFM issues), and the limited capacity at mSAP-capable facilities. Prototype quantities may face longer lead times than production orders because mSAP lines operate most efficiently at volume and may batch smaller orders.

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The Middle Ground — Advanced Subtractive Techniques

Before committing to mSAP, explore whether advanced subtractive techniques can meet your density requirements. The gap between standard subtractive and mSAP is not empty — several process refinements can extend conventional patterning into finer feature ranges.

Ultra-thin copper foils represent the most impactful change. Moving from standard half-ounce (18 micrometer) foil to quarter-ounce (9 micrometer) or even thinner foils (5 micrometer) dramatically reduces the etch depth required and proportionally reduces lateral undercut. A 5 micrometer foil with an etch factor of 3.0 produces only about 1.7 micrometers of undercut per side, which enables subtractive patterning down to approximately 40 micrometers. The trade-off is more difficult handling during lamination and increased susceptibility to scratching during processing.

Etch chemistry optimization can improve the etch factor from the typical 2.5 to 3.0 range toward 3.5 or even 4.0. Acidic cupric chloride etchants with controlled regeneration and high-pressure spray systems achieve the best etch factors by directing etchant preferentially downward into the copper rather than allowing it to pool and attack laterally. The investment is in upgraded etching equipment and tighter chemical process controls rather than entirely different process flows.

Laser direct imaging with high-resolution optics (below 10 micrometer pixel size) improves the photoresist patterning accuracy that feeds into the etch process. If the resist edge is sharper and more precisely placed, the etched feature more accurately reflects the design intent, even if the etch process itself is conventional.

These techniques collectively can extend subtractive processing to 40 to 50 micrometer features on outer layers without requiring the full mSAP process flow, tooling, or material changes. For many designs that are slightly beyond standard subtractive capability but do not require the full density of mSAP, this middle ground offers a cost-effective and lower-risk manufacturing path.

Where the Industry Is Heading

The trajectory is clear. As IC packages continue to shrink pad pitches — driven by chiplet architectures, high-bandwidth memory interfaces, and AI accelerator designs — the printed circuit board that connects those packages must keep pace with finer routing density. The CHIPS Act and similar programs worldwide are accelerating domestic semiconductor manufacturing, and that same investment wave is pulling PCB fabrication capabilities forward.

Several trends are shaping the near-term future of fine-line PCB patterning. Hybrid stackups that combine mSAP layers (for high-density routing near BGA devices) with subtractive layers (for power distribution and low-density signal routing) are becoming more common. This approach applies mSAP cost and complexity only where the density demands it, keeping the majority of the stackup in conventional processing.

Panel-level packaging is blurring the traditional boundary between IC substrate and PCB. Fabricators who invested in mSAP capability are now positioned to compete for packaging work that was previously exclusive to substrate manufacturers. This convergence is expanding the market for mSAP-equipped facilities and is likely to accelerate the adoption of semi-additive processes across the broader PCB industry.

Equipment manufacturers are developing process tools specifically designed for the mSAP transition market — fabricators who have decades of subtractive experience and want to add semi-additive capability without replacing their entire production infrastructure. These tools include modular electroless plating lines, high-resolution direct imaging systems capable of both conventional and mSAP resolutions, and flash etch systems optimized for thin seed removal.

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Choosing the Right Process for Your Design

The decision between subtractive and mSAP is ultimately a routing density decision, and it should be made early in the design cycle rather than discovered during fabrication quoting. Review your BGA breakout requirements, your target layer count, and your signal integrity constraints before completing your stackup definition.

If your finest trace is 75 micrometers or wider on outer layers and 50 micrometers or wider on inner layers, standard subtractive processing is the clear choice. The process is mature, the fabrication partner options are extensive, costs are well understood, and lead times are short.

If your design requires outer layer traces between 40 and 60 micrometers, investigate advanced subtractive processing first. The cost premium over standard subtractive is modest, the material options are broader, and more fabricators can support this range than can offer full mSAP capability.

If your design requires traces below 40 micrometers on any layer, mSAP is the appropriate process. Engage your fabrication partner early, discuss material options, and plan for the DFM adjustments described in this article. The technology is production-proven and the fabrication base capable of delivering mSAP boards is growing, but early engineering collaboration remains essential for a successful outcome.

The goal is not to use the most advanced process available. The goal is to use the most appropriate process — the one that delivers your required density at acceptable cost, yield, and lead time. That decision, made correctly at the design stage, is worth more than any amount of process optimization after the fact.