How to Specify PCB Copper Weight: Current Capacity, Etching Limits, and Stackup Rules

Quick Reference: Copper Weight Selection

Note: Values assume 10C temperature rise on outer layers. Inner layers carry approximately 50% less at same geometry.

The Etch Factor Problem

This is the single most common DFM issue with heavy copper. Every PCB engineer needs to understand it.

When copper is etched, the etchant attacks sideways as well as downward. The ratio of vertical etch depth to lateral undercut is the “etch factor.” For standard chemistry:

• 1oz copper: Etch factor 3:1 to 4:1 (undercut ~9-12um per side)
• 2oz copper: Etch factor 2.5:1 to 3:1 (undercut ~23-28um per side)
• 3oz copper: Etch factor 2:1 to 2.5:1 (undercut ~42-53um per side)
• 5oz copper: Etch factor 1.5:1 to 2:1 (undercut ~88-117um per side)

What this means in practice:

A trace drawn as 5mil (127um) in your Gerber file, fabricated in 3oz copper, will have:

• Top width: 127um - 2 x 50um = ~27um (barely viable)
• Bottom width: 127um (at copper-substrate interface)
• Trapezoidal cross-section

This is why heavy copper demands wider minimum trace widths. Your CAD tool shows rectangular traces, but the fabricated result is trapezoidal.

Fabrication Compensation

Reputable fabricators (including AtlasPCB) apply etch compensation — we widen your traces in the photo tool by the expected undercut amount. But this only works if:

1. Your traces are wide enough that compensation leaves a viable top width
2. Your spaces are wide enough to remain clear after compensation widens adjacent traces
3. You specify copper weight clearly so we know how much to compensate

Never design at minimum trace width for heavy copper without confirming with your fabricator.

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Upload your Gerber files and stackup. We verify trace/space meets etch factor limits for your specified copper weight before production.

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Current Capacity Calculations

The industry standard reference is IPC-2152 (supersedes the older IPC-2221 charts). Key variables:

• Trace width (the primary design knob)
• Copper thickness (your specified weight)
• Allowable temperature rise (typically 10C, 20C, or 30C above ambient)
• Layer position (outer vs inner — inner carries less due to poor heat dissipation)

Outer Layer Current Capacity (10C Rise)

Inner Layer Derating

Inner copper layers are sandwiched in laminate with poor thermal conductivity (~0.3 W/mK for FR-4). Apply these factors:

• Inner layer capacity = Outer capacity x 0.5 (for same 10C rise)
• Or equivalently, double the trace width for inner power planes
• Ground/power planes are exceptions — large copper pours dissipate effectively via thermal vias

Thermal Via Enhancement

For components with exposed thermal pads (QFNs, power MOSFETs), thermal vias connecting the pad to an inner ground plane can increase effective current capacity by 40-60%. AtlasPCB supports via-in-pad with conductive fill (VIPPO) for this application.

Specifying Copper Weight in Your Fab Drawing

Your fabrication drawing (or README/stackup document) must clearly state:

Required Information

1. Copper weight per layer — do not assume fabricator knows your intent
2. Finished copper thickness vs starting copper — important distinction:
   • Starting copper (base foil): What you order (e.g., 1oz = 35um)
   • Finished copper (after plating): Adds ~20-25um from electroless + electrolytic plating on outer layers
   • A “1oz finished” outer layer actually starts as ~0.5oz base foil + plating
3. Whether inner layers include plating — inner layers typically stay at base foil weight (no additional plating unless via holes are plated)

Example Stackup Table (6-Layer, Mixed Copper)

STACKUP ENGINEERING

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Common Mistakes and How to Avoid Them

Mistake 1: Specifying 2oz Everywhere “Just in Case”

Engineers sometimes specify 2oz on all layers for current margin. The consequences:

• Inner signal layers lose fine-trace capability (5/5mil minimum vs 3/3mil)
• Board cost increases 10-20% for the extra copper
• Impedance matching becomes harder (wider traces for same impedance)
• Board weight increases (matters for aerospace/portable)

Fix: Use heavy copper only on power layers. Route signals on 0.5oz or 1oz layers.

Mistake 2: Ignoring Copper Balance

Unequal copper distribution between top/bottom or between inner layers causes board warpage during lamination. The copper on each side creates differential thermal expansion stress.

Rule of thumb: Keep copper fill percentage within 20% between paired layers (L1/L6, L2/L5, etc.). Use copper thieving patterns on sparse layers.

See our detailed guide on copper balancing techniques for quantitative analysis.

Mistake 3: Not Accounting for Plating Thickness on Outer Layers

If your impedance simulation uses 1oz (35um) for the outer layer trace thickness, your manufactured board will be wrong. Outer layers receive 20-25um additional plating during the PTH process. The actual trace thickness is 55-60um, which changes impedance by 3-8%.

Fix: Simulate with finished copper thickness. Ask your fabricator for their typical plating addition.

Mistake 4: Thermal Relief Pads Too Narrow for Heavy Copper

Thermal relief spokes connecting a pad to a power plane must be wide enough to carry current and survive etching:

• 1oz copper: 8mil spoke width minimum
• 2oz copper: 12mil spoke width minimum
• 3oz copper: 16mil spoke width minimum

Narrow spokes in heavy copper etch to nothing, leaving the pad electrically disconnected.

POWER ELECTRONICS

Heavy Copper PCBs for Power Conversion

Motor drives, power supplies, EV chargers -- AtlasPCB fabricates up to 5oz outer / 3oz inner copper with controlled impedance on signal layers.

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Cost Impact Summary

The most cost-effective approach for power-intensive designs: use 2oz outer + 1oz inner with wide power traces, rather than 3oz everywhere with narrow traces. You get equivalent current capacity at lower cost and better signal routing flexibility.

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Related Reading:

• PCB Trace Width and Current Capacity Calculator
• PCB Copper Balancing Techniques
• VIPPO Via-in-Pad Design for Thermal Management
• PCB Stackup Design Guide