Free Engineering Tool
Via Impedance Calculator
Estimate a via's characteristic impedance, parasitic capacitance and inductance from its physical dimensions using the coaxial approximation model. Verify whether your via geometry matches your target system impedance.
Via Impedance Calculator
Enter pad diameter, antipad diameter, via length and Dk. Results update live.
Via Geometry
Via land / capture pad OD
Clearance hole in reference plane
Standard 1.6mm ≈ 62 mil · for stub analysis use signal-to-exit distance
Effective Dk of material surrounding the via barrel
Cross-Section Model
Pad: 24 mil
Antipad: 40 mil
D_pad/D_antipad = coaxial ratio
Z = (60/√εr) × ln(D_ap/D_pad)
Results
Via Characteristic Impedance
⚠ 35Ω from 50Ω — consider adjusting antipad size
Capacitance
0.719 pF
Inductance
0.476 nH
D_ap/D_pad Ratio
1.67
Ideal for 50Ω: ~2.0 in FR-4
BW Estimate
29.6 GHz
Capacitive 3dB bandwidth
50Ω Design Guide (FR-4, Dk≈4.2)
For Z_via ≈ 50Ω in FR-4: D_antipad/D_pad ≈ 2.0. Example: 24 mil pad → 48 mil antipad. Larger antipads raise impedance but reduce plane copper; smaller antipads lower impedance but increase return-path inductance at high speeds.
Coaxial approximation per Bogatin/Johnson. Accuracy is best for isolated vias with uniform dielectric. Real vias have additional fringing capacitance from pad lands on multiple layers, non-uniform Dk, and coupling to nearby vias/planes not captured by this model. For high-speed (>10 Gbps) designs, validate with 3D EM simulation.
The Model
Coaxial approximation for via impedance
A plated via passing through a ground plane looks like a short coaxial transmission line: the via barrel is the center conductor and the antipad clearance is the outer conductor. The formulas below are from Eric Bogatin's "Signal and Power Integrity" and are widely used for first-pass via modeling.
Impedance
Z = (60/√εr) × ln(D_ap/D_pad)The ratio D_ap/D_pad is the dominant tuning variable.
Capacitance
C = 1.41×εr×T / ln(D_ap/D_pad)
T in inches → C in pFLonger vias = more capacitance.
Inductance
L = 5.08×T × (1+ln(D_ap/D_pad))
T in inches → L in nHLarger antipad = more inductance.
FAQ
Via impedance, answered
What determines a via's impedance?
The ratio of antipad to pad diameter and the surrounding Dk. Z = (60/√εr) × ln(D_ap/D_pad). For 50Ω in FR-4, target D_ap/D_pad ≈ 2.0.
How much capacitance does a typical via add?
A 62 mil via in FR-4 with 24 mil pad / 40 mil antipad adds about 0.5–0.7 pF. At 50Ω, each pF contributes ~7 ps of added delay.
Why does via impedance matter?
Mismatched vias reflect signal energy, degrading return loss and eye opening. At multi-gigabit rates, via impedance discontinuities accumulate across the channel.
How accurate is the coaxial model?
Good for first-pass design (±10–15%). It does not account for pad capacitance on multiple layers, non-circular clearances, nearby vias, or via fill. For 10 Gbps+ validation, use 3D EM simulation.
Optimized via design, built right
Controlled-impedance vias, precise antipad sizing, back-drilling — engineer-reviewed and TDR-verified. 1-piece MOQ.