Buried Capacitance in PCBs: Embedded Layers for PDN

Introduction: The Power Delivery Challenge in Modern PCBs

Every digital IC on a printed circuit board demands clean, stable power. As clock frequencies push past 1 GHz and edge rates drop below 100 ps, the power delivery network (PDN) faces increasingly stringent impedance targets — often below 10 mΩ across a bandwidth spanning DC to several gigahertz. Traditional approaches rely on arrays of discrete multilayer ceramic capacitors (MLCCs) placed around BGA packages, but this strategy encounters fundamental physical limits: the parasitic inductance of SMD capacitor mounting (typically 0.5–1.5 nH per cap) creates anti-resonance peaks that can amplify noise rather than suppress it.

Buried capacitance — also called embedded capacitance or planar capacitance — offers an elegant alternative. By incorporating ultra-thin dielectric layers between power and ground planes within the PCB stackup, designers create a distributed capacitor that provides broadband decoupling with loop inductance measured in picohenries rather than nanohenries. This article examines the physics, materials, design methodology, fabrication requirements, and practical performance of buried capacitance technology for PDN optimization.

For a broader view of embedding passive components directly into PCB substrates, see our guide on embedded component PCB technology.

Physics of Planar Capacitance

Parallel-Plate Fundamentals

The capacitance between two conductive planes separated by a dielectric follows the parallel-plate equation:

C = ε₀ × εᵣ × A / d

Where:

• ε₀ = 8.854 × 10⁻¹² F/m (permittivity of free space)
• εᵣ = relative dielectric constant of the insulating layer
• A = overlapping area of the power and ground planes
• d = dielectric thickness

Two variables are under the designer’s direct control: dielectric thickness (d) and material selection (εᵣ). Reducing d from a standard 4-mil core to a 1-mil core quadruples the capacitance per unit area. Selecting a high-Dk material further multiplies the effect.

Capacitance Density by Material and Thickness

For a 100 cm² (≈15.5 in²) plane pair — typical for a mid-size BGA footprint and its surrounding power island — a 1-mil FR-4 core delivers approximately 9.5 nF of distributed capacitance. While this seems modest compared to a single 100 nF MLCC, the critical advantage is the delivery mechanism: the planar capacitor has loop inductance below 50 pH, making it effective at frequencies where discrete capacitors have already become inductive.

Impedance Behavior Across Frequency

A discrete 100 nF 0402 MLCC with 0.8 nH mounting inductance resonates at approximately 180 MHz. Below resonance it behaves as a capacitor; above resonance it becomes an inductor that actually increases PDN impedance. In contrast, the buried capacitance layer maintains capacitive behavior well beyond 1 GHz because the current path between planes is essentially a transmission line with sub-millimeter height — the inductance is geometrically negligible.

The combined effect of discrete bulk capacitors (effective DC–50 MHz), buried capacitance (effective 50 MHz–1 GHz+), and on-die capacitance (effective above 500 MHz) creates a cascaded decoupling strategy with overlapping frequency coverage and no problematic anti-resonance gaps.

For more on this cascaded decoupling approach, see our article on PCB power integrity and decoupling.

Materials for Buried Capacitance

Standard Thin-Core FR-4

The most accessible approach uses standard FR-4 laminate cores milled or pressed to 1–2 mil thickness. Major laminate suppliers including Isola, Panasonic, and Shengyi offer thin cores compatible with conventional PCB processing:

Standard thin FR-4 is cost-effective and widely available, making it the default choice for most buried capacitance implementations. The tradeoff is moderate capacitance density — increasing Dk requires specialized materials.

High-Dk Dielectric Systems

For applications demanding higher capacitance density, several engineered dielectric systems are available:

Ceramic-Filled Resin Systems: Materials like 3M ECM (Embedded Capacitance Material) use barium titanate (BaTiO₃) particles dispersed in epoxy resin to achieve Dk values of 16–25. These are processed similarly to standard prepregs but require careful lamination pressure control to maintain uniform thickness.

Thin-Film Deposited Dielectrics: Sputtered or CVD-deposited layers of materials like hafnium oxide (HfO₂, Dk ≈ 25) or tantalum pentoxide (Ta₂O₅, Dk ≈ 26) can achieve sub-micron thicknesses on copper foil before lamination. These exotic approaches yield extremely high capacitance density (>10 nF/cm²) but at significantly higher cost.

Polymer-Ceramic Composites: Compounds blending high-Dk ceramic powders (BaTiO₃, CaTiO₃) into polyimide or epoxy matrices offer Dk values of 10–40 with conventional PCB processing compatibility. Companies like Oak-Mitsui (FaradFlex) have commercialized these for volume production.

Material Selection Decision Matrix

Stackup Design for Buried Capacitance

Placement in the Layer Stack

The buried capacitance core should be positioned as close as possible to the IC die — typically as the innermost power/ground plane pair in the stackup. In a 12-layer board, layers 5 and 6 (or 6 and 7) separated by a 1-mil core would form the embedded capacitor, directly beneath the BGA field.

A representative 12-layer stackup with buried capacitance:

For detailed guidance on layer arrangement and impedance planning, refer to our PCB stackup design guide.

Design Rules and Constraints

Plane Overlap Area: Maximize the overlapping area of the power and ground planes surrounding the target IC. Avoid splits, cutouts, and thermal relief spokes in the buried capacitance region — every square millimeter of removed copper reduces the effective capacitance.

Via Anti-Pad Clearance: Signal vias passing through the buried capacitance planes create anti-pads that reduce effective area. For a 10-mil drill with 20-mil anti-pad, each via removes approximately 2 mm² of plane area. In dense BGA fields with 1-mm pitch, this can reduce effective capacitance by 15–25%.

Power Island Design: When multiple voltage rails share the same plane layers, the buried capacitance benefit applies only to the rail with the largest continuous copper area. Consider dedicating the thin-core pair exclusively to the most noise-sensitive power rail (typically the core voltage of the primary processor).

Plane Copper Weight: Use 1 oz (35 µm) or heavier copper for the planes forming the buried capacitor. Thicker copper reduces plane resistance, lowering the resistive component of PDN impedance. It also improves current-carrying capacity for high-power rails.

PDN Simulation and Target Impedance

Target Impedance Methodology

The target impedance for a PDN is estimated as:

Z_target = V_rail × Ripple% / I_transient

For a 1.0 V core rail with 3% allowed ripple and 5 A transient current:

Z_target = 1.0 × 0.03 / 5.0 = 6 mΩ

This 6 mΩ ceiling must be maintained from DC through the maximum frequency of interest (typically 3–5× the clock frequency). Buried capacitance is the primary tool for achieving this target in the 50 MHz to 1 GHz range.

Simulation Workflow

Modern PDN analysis tools (Ansys SIwave, Cadence Sigrity PowerSI, Keysight ADS) model the buried capacitance layer as a distributed parameter element:

1. Import stackup with accurate thin-core dielectric properties (Dk, Df, thickness)
2. Define via models with padstack geometry for accurate anti-pad representation
3. Place discrete capacitor models with frequency-dependent SPICE data from MLCC vendors
4. Run AC impedance sweep from 1 kHz to 10 GHz at each power pin
5. Iterate: Adjust discrete cap count, placement, and stackup until Z_target is met across bandwidth

Typical simulation results show that adding a 1-mil buried capacitance core reduces the number of discrete 100 nF MLCCs needed by 30–50% while simultaneously eliminating anti-resonance peaks between 200 MHz and 800 MHz.

Case Study: FPGA Power Delivery

A Xilinx UltraScale+ FPGA design with 0.85 V VCCINT rail, 40 A load, and 15 A/ns transient demand:

The buried capacitance approach eliminated the anti-resonance peak entirely while reducing component count by 40–60%, freeing BGA escape routing channels and reducing assembly cost.

Fabrication Process Considerations

Thin-Core Handling

Processing 1-mil (25 µm) cores requires specialized handling throughout the fabrication flow:

Incoming Inspection: Thin cores are inspected for thickness uniformity using non-contact optical gauging. Thickness tolerance is typically ±10% (±2.5 µm for a 1-mil core), compared to ±5% for standard cores. Any wrinkles, dents, or contamination can cause catastrophic yield loss.

Drilling: Vias through the buried capacitance region must be drilled with tight tolerances to prevent drill wander that could create shorts between the closely spaced planes. Laser drilling is preferred for microvias; mechanical drilling requires sharp bits and controlled feed rates.

Lamination: The thin core must maintain uniform thickness during lamination. Excessive resin flow from adjacent prepregs can displace the core, creating thickness variations that cause local capacitance non-uniformity. Controlled-flow prepregs and optimized press cycles (temperature ramp rate, pressure profile) are critical.

Registration: With only 1 mil of dielectric between planes, layer-to-layer registration requirements tighten significantly. Misregistration that would be harmless with standard spacing could create localized thin spots or shorts. Target registration accuracy is ≤1 mil for buried capacitance layers.

Quality Control and Testing

Cross-Section Analysis: Microsection inspection verifies dielectric thickness uniformity at multiple locations. The standard acceptance criterion per IPC-6012 Class 3 is minimum dielectric spacing of 0.5 mil (12.7 µm) after processing.

Capacitance Measurement: Embedded capacitance can be verified by LCR meter measurement between the power and ground plane nets at the board level. Expected values should match simulation within ±20%, accounting for anti-pad area reduction and edge effects.

Insulation Resistance: Hi-pot testing between the buried capacitance planes verifies dielectric integrity. Test voltage is typically 250–500 VDC for a 1-mil dielectric, with minimum insulation resistance of 10 MΩ.

Thermal Cycling: Reliability qualification includes thermal cycling (-55°C to +125°C, 1000 cycles) to verify that differential CTE between copper planes and thin dielectric does not cause delamination or cracking. Properly processed buried capacitance layers routinely pass this requirement.

Performance Benchmarks and Real-World Data

Measured PDN Impedance Improvement

Published data from multiple sources confirms the effectiveness of buried capacitance:

Cost-Benefit Analysis

The economic case for buried capacitance involves balancing material cost increases against component and assembly savings:

Cost Increases:

• Thin-core material premium: +$0.50–$2.00 per panel (FR-4); +$3.00–$15.00 per panel (high-Dk)
• Fabrication process adder: +5–15% for handling and lamination controls
• Yield impact: 2–5% lower initial yield during process qualification

Cost Savings:

• Discrete capacitor reduction: 50–100 fewer MLCCs × $0.005–$0.02 each = $0.25–$2.00 per board
• Assembly time reduction: Fewer placements reduce SMT cycle time
• Board area savings: Eliminated cap pads free routing space, potentially enabling smaller board size or fewer layers
• Reliability improvement: Fewer solder joints reduce field failure modes

For high-volume production (>10,000 units), the breakeven point is typically reached within the first production run. For low-volume, high-performance applications (servers, networking, aerospace), the performance improvement alone justifies the cost.

Design Guidelines and Best Practices

When to Use Buried Capacitance

Buried capacitance is most beneficial when:

• Clock frequencies exceed 500 MHz or edge rates are below 200 ps
• PDN target impedance is below 15 mΩ
• BGA pitch is ≤0.8 mm, limiting space for discrete capacitors
• The design uses multiple high-current power rails requiring broadband decoupling
• EMI reduction is a critical design goal (planar capacitance also reduces plane-edge radiation)

When Standard Decoupling Suffices

Buried capacitance may not be justified when:

• Operating frequencies are below 200 MHz with slow edge rates
• The board has ample area for discrete decoupling capacitors
• PDN target impedance is above 50 mΩ
• The design is cost-sensitive and produced in low volume
• The PCB fabricator lacks experience with thin-core processing

Design Checklist

1. Define target impedance for each power rail from DC to maximum frequency of interest
2. Select dielectric material based on required capacitance density and budget
3. Position buried cap core as close to the IC mounting side as the stackup allows
4. Maximize plane overlap — avoid unnecessary splits, islands, or cutouts in the capacitor region
5. Minimize anti-pad area — use HDI microvias where possible to reduce plane perforation
6. Simulate the complete PDN including discrete caps, buried capacitance, IC package model, and on-die capacitance
7. Specify fabrication requirements clearly: core thickness, tolerance, material, and test criteria
8. Verify in production with capacitance measurement and cross-section analysis

Compatibility with HDI and High-Speed Design

Buried capacitance integrates naturally with HDI (High Density Interconnect) fabrication techniques. Stacked microvias, which are drilled by laser and plated sequentially, create smaller anti-pads than through-hole vias, preserving more plane area for capacitance. The combination of buried capacitance with high-speed PCB design practices — controlled impedance routing, return path continuity, and signal integrity simulation — creates a comprehensive approach to managing both power and signal quality in demanding applications.

Emerging Trends and Future Directions

Ultra-Thin Dielectrics Below 0.5 mil

Research into sub-12 µm dielectrics using advanced polymer-ceramic composites promises capacitance densities above 1 nF/cm² with conventional PCB processing. These materials are currently in qualification at several Asian laminate manufacturers, with production availability expected by 2027.

Integration with Embedded Die Technology

Combining buried capacitance layers with embedded die packaging — where bare silicon is laminated directly into the PCB — creates extremely short power delivery paths. The die-to-plane distance drops from millimeters (through BGA solder balls and package substrate) to tens of micrometers, reducing loop inductance by an order of magnitude.

Additive Manufacturing Approaches

Inkjet-printed high-Dk dielectric layers and aerosol-deposited ceramic films enable selective capacitance deposition — placing high capacitance only where needed rather than across the entire plane pair. This targeted approach maximizes capacitance density at IC power pins while reducing material cost.

Conclusion

Buried capacitance technology represents a mature, production-proven approach to PDN optimization that directly addresses the limitations of discrete decoupling capacitors at high frequencies. By incorporating thin dielectric cores between power and ground planes, designers achieve broadband impedance reduction, eliminate anti-resonance peaks, reduce component count, and improve overall system reliability.

The key to successful implementation lies in proper material selection, simulation-guided stackup design, and close collaboration with a PCB fabricator experienced in thin-core processing. As operating frequencies continue to rise and package densities increase, buried capacitance will transition from a competitive advantage to a design necessity.

Ready to implement buried capacitance in your next design? Upload your Gerbers for a free engineering review — our engineering team will evaluate your stackup and recommend the optimal embedded capacitance solution for your application.