PCB Design Rule Check (DRC): Complete Manufacturability Checklist for Engineers

Introduction: Why DRC Is Non-Negotiable

Every PCB design contains thousands of geometric relationships — trace-to-trace clearances, drill-to-copper distances, pad dimensions relative to holes, copper-to-board-edge margins. A complex 8-layer design might have 50,000+ individual checkable constraints.

Missing even one critical violation can result in:

• Opens: Traces etched too narrow break during fabrication
• Shorts: Inadequate clearance between conductors allows copper bridging
• Drill breakout: Holes positioned too close to copper features cause unintended connections
• Assembly failures: Solder mask dams too narrow allow solder bridging between pads
• Yield loss: Marginal dimensions pass at fabricator but fail at 20–40% rate during production

A thorough DRC with correct manufacturer constraints is the single most effective step you can take to prevent costly respins. Industry data shows that designs submitted with proper DRC reduce NPI (New Product Introduction) cycle time by 2–3 weeks on average.

Category 1: Clearance Rules

Clearance rules ensure adequate spacing between all conductive features to prevent electrical shorts and meet dielectric withstand requirements.

Trace-to-Trace Clearance

Voltage-Dependent Clearance (IPC-2221B)

For circuits exceeding 50V, clearance must increase based on working voltage:

Pad-to-Pad Clearance

Adjacent component pads require sufficient spacing for:

• Solder mask dam between pads (minimum 75 μm mask web)
• Probe access for in-circuit testing (ICT)
• Rework iron access for component replacement

Minimum pad-to-pad: component pad edge to adjacent pad edge ≥ 150 μm (including mask expansion)

Copper-to-Board-Edge Clearance

Category 2: Width Rules

Minimum Trace Width

Neck-Down Rules

Trace width may reduce (“neck down”) when routing between tight-pitch BGA pads. Rules:

• Maximum neck-down length: 2× pad pitch (e.g., 1.6 mm for 0.8mm pitch BGA)
• Neck-down width ≥ 60% of nominal trace width
• Impedance discontinuity from neck-down: verify with field solver if length > λ/20 at signal bandwidth

Current-Carrying Capacity

DRC should enforce minimum widths based on current requirements (IPC-2152):

• External layer: 1A requires ~250 μm (10 mil) at 1 oz copper for 20°C rise
• Internal layer: 1A requires ~300 μm (12 mil) at 1 oz copper for 20°C rise
• Add 50% margin for production tolerances

Category 3: Annular Ring Rules

The annular ring is the copper pad remaining after a drill hole is made. Insufficient annular ring causes drill breakout (hole partially outside pad), creating unreliable connections.

Minimum Annular Ring Dimensions

Calculation

Annular ring = (Pad diameter - Drill diameter) / 2

Example: 0.6mm pad with 0.3mm drill = (600-300)/2 = 150 μm ring ✓

Include registration tolerance: Actual annular ring = Designed ring - Registration error

• Standard registration: ±50 μm → Effective ring = 150 - 50 = 100 μm minimum achieved

Tangency and Breakout

IPC-6012 defines three conditions:

• Full annular ring: Hole completely within pad (ideal)
• Tangent: Hole edge touches pad edge (Class 1/2 acceptable)
• Breakout: Hole extends beyond pad (Class 3: max 90° of breakout)

Configure DRC to flag any via where minimum ring < required_ring + registration_tolerance.

Category 4: Drill Rules

Mechanical Drill Constraints

Laser Drill (Microvia) Constraints

Aspect Ratio Enforcement

Aspect ratio = Board thickness / Drill diameter

A 1.6mm board with 0.2mm drill = 8:1 aspect ratio. This is achievable but represents an advanced capability. DRC should flag:

• Standard process: aspect ratio > 8:1
• Via fills: aspect ratio > 6:1 (difficult to void-free fill)
• HDI builds: verify with fabricator for each specific stackup

Category 5: Plane/Pour Rules

Copper Pour Clearance

Ground and power planes must maintain adequate clearance to signal vias/pads passing through:

Thermal Relief Design

Through-hole component pads connected to planes require thermal relief patterns for solderability:

• Spoke width: ≥ 200 μm (≥ trace minimum width)
• Spoke count: 4 spokes for standard components; 2 spokes for large thermal pads (to improve heat sinking)
• Relief gap: Same as anti-pad clearance (200–250 μm)
• Direct connect: BGA pads and thermal pads where maximum thermal conductivity is needed

Copper Balance

DRC should flag copper coverage imbalance between layers:

• Target: All layers within ±15% copper coverage of each other
• Critical threshold: >30% imbalance causes bow/twist during lamination
• Solution: Add copper thieving/hatching to low-coverage areas

Category 6: Solder Mask and Silkscreen Rules

Solder Mask Dam Width

The solder mask web between adjacent pad openings must be wide enough to prevent mask collapse during coating:

Rule: If calculated mask dam < minimum, specify NSMD (Non-Solder-Mask-Defined) pads and remove mask between the pad cluster entirely.

Solder Mask Expansion

Standard mask opening = Pad size + expansion per side:

• Standard: +50 μm (2 mil) per side
• Fine-pitch (≤0.5mm): +25 μm (1 mil) per side
• BGA: Often 1:1 (mask opening = pad size) for NSMD

Silkscreen Rules

Setting Up DRC in Your EDA Tool

Altium Designer

1. Navigate to Design → Rules → PCB Rules and Constraints
2. Create rule categories matching the six categories above
3. Set priorities: Manufacturing rules > electrical rules > signal integrity rules
4. Enable Online DRC for real-time violation highlighting
5. Import manufacturer constraint file if available (.RUL format)

KiCad 8+

1. Open Board Setup → Design Rules → Constraints
2. Define net classes with per-class clearance and width rules
3. Use Custom Rules (.kicad_dru) for complex conditional checks:

(rule "BGA neck-down"
  (condition "A.NetClass == 'BGA_SIGNALS' && A.insideArea('BGA_FANOUT')")
  (constraint track_width (min 0.075mm)))

4. Run DRC via Inspect → Design Rules Checker

Cadence Allegro

1. Set up Physical and Spacing constraints in Constraint Manager
2. Define constraint regions for area-specific rules (BGA region, high-voltage region)
3. Configure DRC batch run with output to HTML report
4. Enable real-time DRC with immediate visual markers

Common DRC Violations and Fixes

Top 10 Most Frequent Violations

1. Clearance violation at BGA fanout: Reduce trace width with neck-down rule; or switch to HDI via-in-pad
2. Annular ring too small on vias: Increase pad size or reduce drill diameter
3. Trace too close to board edge: Move traces inward or increase board outline
4. Solder mask dam too narrow: Switch to NSMD pad definition or increase pad pitch
5. Unconnected copper fragments: Add copper pour with minimum area threshold (remove islands < 0.5 mm²)
6. Acid trap (acute angle junction): Chamfer trace junctions to >90° angles
7. Copper sliver: Thin copper fragments (<75 μm wide) that detach during etching — increase clearance or merge with adjacent copper
8. Drill-to-copper violation: Increase anti-pad or move via away from trace
9. Missing thermal relief on PTH pads: Add relief pattern in plane layers
10. Silk over exposed pad: Auto-clip silkscreen at pad boundaries

When to Waive DRC Violations

Some violations are intentional and acceptable:

• Controlled-impedance traces narrower than standard minimum (verified by calculation)
• Edge connectors with copper extending to board edge
• RF structures with non-standard geometries (spiral inductors, coupled lines)
• Deliberate clearance reduction in specific zones (with fabricator approval)

Always document waivers in your design notes and confirm with your fabricator before release.

Further Reading

• PCB Design Rules: Trace Width and Spacing — Detailed trace geometry guidelines
• PCB Annular Ring and IPC Standards — Deep dive into ring requirements
• PCB Solder Mask Dam Design — Mask-specific DFM rules
• PCB Aspect Ratio and Via Design — Drill capability limits

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