IC Substrate vs HDI PCB: Understanding Substrate-Like PCB (SLP) Technology for Advanced Semiconductor Packaging

Introduction: The Convergence of PCB and Semiconductor Packaging

The boundary between PCB fabrication and IC substrate manufacturing is dissolving. As semiconductor packages grow larger (50×50mm+ interposers), use finer bump pitches (≤0.4mm), and demand higher I/O counts (5,000+ connections), the PCB that hosts these packages must match their density at the interface. Simultaneously, IC substrate manufacturers are scaling to panel-level production that resembles PCB manufacturing more than traditional strip-based substrate fabrication.

This convergence has created Substrate-Like PCB (SLP)—a technology that borrows IC substrate processes (mSAP, ABF dielectrics, laser direct imaging) and applies them at PCB scale, achieving 20-30μm trace geometries that bridge the gap between traditional HDI (50-75μm) and IC substrates (2-15μm).

Understanding where each technology applies—and where they overlap—is essential for any engineer designing high-density electronics, from 5G smartphones to AI accelerator systems. For foundational HDI knowledge, see our [HDI PCB technology guide]/blog/hdi-pcb-technology/).

Technology Comparison: Three Levels of Interconnect

IC Substrate (BGA Substrate / Flip-Chip Substrate)

Function: Provides first-level interconnect between silicon die and the main PCB. Redistributes ultra-fine die bumps (40-130μm pitch) to BGA balls (0.4-1.0mm pitch).

Key specifications:

• Trace/space: 2-15μm (advanced) to 15-30μm (mainstream)
• Layer count: 4-16 build-up layers
• Via diameter: 20-50μm (laser-drilled)
• Dielectric: ABF (Ajinomoto Build-up Film), BT (Bismaleimide Triazine)
• Dielectric thickness: 15-35μm per layer
• Process: Full SAP (Semi-Additive Process) or modified SAP
• Manufacturing environment: Cleanroom (Class 1000-10000)
• Panel size: Strip format (typically 70×255mm or similar)

Manufacturers: Ibiden, Shinko, Samsung Electro-Mechanics, Unimicron, AT&S, Kinsus

HDI PCB (High-Density Interconnect PCB)

Function: Provides board-level interconnect for all components. Routes signals, power, and ground between multiple ICs, connectors, and passive components.

Key specifications:

• Trace/space: 50-75μm (production), 40μm (advanced)
• Layer count: 8-24+ layers (including build-up and core)
• Via diameter: 75-150μm ([laser blind vias]/blog/pcb-laser-drilling-microvia-technology/)), 200μm+ (mechanical through-vias)
• Dielectric: FR-4, [high-speed laminates]/blog/high-frequency-pcb-substrate-selection-dk-df/) (Megtron 6/7, IS415)
• Dielectric thickness: 40-100μm (build-up), 100-200μm (core)
• Process: Subtractive etch (standard) or mSAP (advanced HDI)
• Manufacturing environment: Standard PCB fab (controlled but not cleanroom)
• Panel size: 18×24” or 21×24” (production panels)

Manufacturers: TTM, AT&S, Unimicron, Compeq, Ibiden, ZDT, Shennan Circuits

Substrate-Like PCB (SLP)

Function: Replaces standard HDI in applications where routing density exceeds conventional HDI capability. Often used in smartphone main boards and wearable devices.

Key specifications:

• Trace/space: 20-35μm (production)
• Layer count: 6-12 build-up layers (usually coreless)
• Via diameter: 40-75μm (laser-drilled)
• Dielectric: ABF or enhanced build-up film
• Dielectric thickness: 20-40μm per layer
• Process: mSAP (modified Semi-Additive Process)
• Manufacturing environment: Enhanced cleanroom (Class 10000)
• Panel size: Large panel format (similar to PCB panels)

Manufacturers: AT&S, Unimicron, Samsung Electro-Mechanics, Zhen Ding Technology

Manufacturing Process Comparison

Subtractive Process (Standard HDI)

The traditional PCB approach:

1. Start with copper-clad laminate (12-18μm Cu)
2. Apply photoresist, expose, develop
3. Etch away unwanted copper
4. Strip resist

Fundamental limitation: Etch undercut. As etchant dissolves copper vertically, it also attacks sideways beneath the resist. With 12μm copper, undercut reaches 6-9μm per side, setting minimum L/S at ~40-50μm for reliable production.

Etch factor: Ratio of etch depth to undercut. Typical production achieves 2.5-3.5:1. For 12μm copper:

• Minimum space = 2 × (12μm ÷ 3) = 8μm theoretical + registration + process margin = ~40μm practical

Semi-Additive Process (SAP) — IC Substrates

The semiconductor packaging approach:

1. Start with bare dielectric (ABF film, no copper)
2. Deposit thin seed layer by sputtering or electroless Cu (0.1-0.5μm)
3. Apply photoresist, expose, develop (pattern = traces)
4. Electroplate copper into resist openings (5-15μm)
5. Strip resist
6. Flash-etch seed layer (0.1-0.5μm removal—minimal undercut)

Advantage: Near-zero etch undercut because only 0.1-0.5μm seed layer is etched. Trace width defined by photolithography resolution, not etch chemistry. Enables 2-5μm traces in production.

Limitation: Slow, expensive, requires ultra-clean environment. Sputtered seed layers need vacuum equipment. Extremely thin copper handling requires specialized automation.

Modified Semi-Additive Process (mSAP) — SLP

The bridge technology:

1. Laminate ultra-thin copper foil (1.5-3μm) onto build-up dielectric
2. Apply photoresist, expose, develop (pattern = traces)
3. Electroplate copper into resist openings (10-20μm)
4. Strip resist
5. Flash-etch the thin foil layer (1.5-3μm removal)

Advantage over subtractive: Only 1.5-3μm of copper to etch through means undercut is <1μm per side, enabling 20-30μm traces with standard UV lithography.

Advantage over full SAP: No vacuum sputtering needed. Uses copper foil lamination (PCB-compatible equipment). Lower cleanroom requirements. Compatible with large PCB panel formats.

Trade-off: Slightly wider traces than full SAP (20μm vs 2μm minimum) but dramatically lower cost and higher throughput.

Material Systems: Why Dielectrics Matter

ABF (Ajinomoto Build-up Film)

The dominant IC substrate and SLP dielectric:

• Surface roughness: Ra < 0.3μm (vs. 3-5μm for FR-4 prepreg)
• Thickness control: ±2μm on 25μm films
• CTE: 30-60 ppm/°C (above Tg)
• Dk at 10 GHz: 3.0-3.4
• Df at 10 GHz: 0.008-0.015
• Tg: 190-210°C

ABF’s ultra-smooth surface enables fine-line copper adhesion at trace widths below 30μm. Rough surfaces trap copper in pits, making consistent narrow traces impossible.

BT (Bismaleimide Triazine)

Traditional IC substrate core material:

• Used as rigid core in build-up substrates
• Higher Tg than FR-4 (250-280°C)
• Lower CTE (12-14 ppm/°C X/Y)
• Good dimensional stability during sequential processing
• Being displaced by coreless construction in advanced substrates

FR-4 and High-Speed Laminates

Standard HDI PCB materials:

• Standard FR-4: Dk 4.2-4.5, Df 0.015-0.025 @ 1GHz. Adequate for designs ≤10 Gbps
• Mid-loss (Megtron 4 class): Dk 3.7-3.9, Df 0.005-0.008. For 10-28 Gbps
• Ultra-low-loss (Megtron 7 class): Dk 3.3-3.5, Df 0.002-0.003. For 56+ Gbps

Standard FR-4 prepreg cannot support mSAP due to glass fiber reinforcement creating surface roughness. SLP uses unreinforced ABF-type films for build-up layers, sometimes over an FR-4 core for mechanical support.

Design Rule Comparison

Application Boundaries: When to Use What

Use Standard HDI When:

• Trace/space ≥50μm satisfies routing density
• Cost optimization is primary driver
• Board requires thick copper for power delivery
• Mechanical drilling is acceptable for through-vias
• Standard FR-4 Tg is adequate
• Panel utilization and volume pricing matter

Use SLP When:

• Fan-out from ≤0.4mm pitch packages in limited area
• Layer count reduction saves more than SLP premium
• Smartphone/wearable form factor constraints
• Need 20-35μm traces but not IC-substrate-class (2-8μm)
• High-frequency performance benefits from thin, smooth dielectrics
• Volume justifies mSAP equipment investment (>100k sqft/month typical)

Use IC Substrate When:

• Direct die attachment (flip-chip, wire bond)
• Redistribution of die-level bumps (<100μm pitch)
• Interposer function (2.5D packaging)
• Known-good-die testing infrastructure required
• Controlled collapse chip connection (C4) or micro-bump interface

The SLP Manufacturing Challenge

Why SLP Is Hard

SLP occupies an uncomfortable middle ground:

• Not quite IC substrate: Lacks the extreme cleanliness and precision of wafer-fab heritage
• Not quite PCB: Requires tighter process control than standard PCB fabs can deliver
• Investment threshold: mSAP line equipment costs $50-100M+
• Yield sensitivity: 20μm traces on large panels amplify defect impact
• Limited supplier base: <10 factories globally can produce SLP at scale

mSAP Process Control Challenges

Ultra-thin foil handling: 1.5-3μm copper foil is fragile and wrinkles easily during lamination. Requires specialized vacuum lamination presses and low-tension handling systems.

Resist resolution: 20μm L/S requires resist systems originally developed for IC lithography, including LDI (Laser Direct Imaging) at ≤5μm resolution rather than standard PCB photo tools.

Flash etch uniformity: Etching exactly 1.5-3μm uniformly across a 500×600mm panel within ±0.5μm requires advanced spray etch systems with real-time thickness monitoring.

Defect density: At 20μm L/S, a single 10μm particle causes an open or short. Particle control requirements approach IC substrate levels—HEPA filtration, operator gowning, material handling protocols.

Yield vs. Density Trade-off

Yield decreases exponentially with finer features on larger panels:

This yield curve explains why SLP commands 5-10× the price of standard HDI per unit area.

Market Dynamics: The $4.24 Billion SLP Opportunity

The substrate-like PCB market is growing rapidly, driven by:

5G Smartphone Adoption

• AiP (Antenna-in-Package) modules require 25-30μm traces for mmWave antenna feeds
• SoC fan-out demands finer routing than HDI can provide
• Board size reduction pressure in foldable phone designs

AI Edge Computing

• NPU packages with 1000+ I/Os on mobile form factors
• Inference engines requiring high-speed interconnect in limited area
• Sensor fusion SoCs with mixed-signal routing density

Advanced Packaging Ecosystem

• Fan-out panel-level packaging (FOPLP) creates substrate demand
• Chiplet integration requires high-density redistribution
• Heterogeneous integration places multiple die on shared substrates

Automotive Advanced Driver Assistance

• ADAS sensor fusion requires dense, high-speed PCBs
• Radar processor packages growing in I/O count
• Automotive quality requirements (AEC-Q100) now expected on substrates

Design Implications for Engineers

Escape Routing from Fine-Pitch BGAs

The most common trigger for SLP adoption is BGA escape routing:

A 15×15mm BGA at 0.4mm pitch has 1369 balls (37×37 array). After removing ground/power balls that connect to internal planes, approximately 500-700 signal balls require routing to board-level interconnect.

With 50μm L/S (standard HDI):

• Can route 1 trace between via pads (1 track per channel)
• Requires 6-8 routing layers for escape
• Total board thickness increases significantly

With 25μm L/S (SLP):

• Can route 2-3 traces between via pads
• Escape accomplished in 2-4 layers
• Board stays thin, layer count decreases

The layer count reduction from SLP often more than offsets the per-layer cost premium.

Signal Integrity at SLP Geometries

Thinner dielectrics and narrower traces change electromagnetic behavior:

• Impedance control: 50Ω requires ~25μm trace on 20μm dielectric (vs. 75μm trace on 100μm dielectric in standard HDI). Tolerances tighter.
• Crosstalk: Reduced trace spacing increases coupling. Requires more careful routing rules.
• Loss: Thinner copper increases resistive loss. Must account for skin depth at high frequencies.
• Return path: Via transitions more critical with thinner dielectrics—field coupling to adjacent layers increases.

Thermal Management in Thin Substrates

SLP’s thin construction (total thickness 0.3-0.6mm) limits thermal spreading:

• Reduced copper volume for heat conduction
• Smaller thermal vias possible but less effective
• Critical for high-power applications (processor packages dissipating 5-15W)
• May require heat spreader attachment or thermal interface material design

Future Trajectory: Panel-Level Substrate Integration

The industry is moving toward convergence:

IC substrate makers are scaling to panel formats (500×500mm+) to reduce cost PCB makers are adopting mSAP and ABF for SLP production

Eventually, the distinction between “IC substrate” and “PCB” may become purely a matter of line/space capability rather than a fundamental technology difference. The manufacturing platform—panel-level processing with semi-additive metallization on smooth dielectrics—is converging.

Key trends to watch:

• Glass core substrates replacing organic cores for dimensional stability
• SAP on glass interposers for 2.5D packaging
• Hybrid build-up (ABF over glass core) for combined stiffness and density
• AI-assisted defect inspection enabling tighter process windows

Conclusion: Matching Technology to Application

The choice between IC substrate, SLP, and standard HDI is ultimately a design optimization problem: achieve the required electrical performance and routing density at minimum cost while meeting reliability requirements.

Decision framework:

1. Can standard HDI (50μm L/S) route your design? → Use HDI (lowest cost)
2. Can you escape BGAs with 35μm L/S? → Consider advanced HDI with mSAP capability
3. Do you need 20-30μm L/S? → SLP (higher cost, requires qualified supplier)
4. Do you need direct die attachment or <20μm L/S? → IC substrate (semiconductor packaging)

As advanced packaging continues pushing package I/O density, the demand for SLP will only grow. Engineers who understand the technology boundaries and design implications of each interconnect level will make better architecture decisions—choosing the right technology for each application rather than over-specifying (wasting cost) or under-specifying (hitting routing limits in layout).

AtlasPCB manufactures advanced HDI PCBs up to 32 layers with any-layer interconnect capability. For designs requiring SLP or IC substrate interfaces, our engineering team provides [stackup consultation]/blog/pcb-stackup-design-guide/) and supplier coordination. Contact us to discuss your high-density interconnect requirements.

Further Reading

• [HDI PCB Design for 5G Antenna Integration: Signal Integrity Challenges in Millimeter-Wave Applications]/blog/hdi-5g-antenna-integration-pcb-design/)
• [Any-Layer HDI PCB Design: When to Go Beyond 2+N+2 and How to Optimize for Wearables and SiP Modules]/blog/any-layer-hdi-pcb-design-wearable-sip/)
• [Via-in-Pad Design: Filled, Capped, and Plated Over — Complete Guide]/blog/via-in-pad-design/)
• [PCB Copper Plating Process: Electroless vs Electrolytic Copper for HDI Vias and High-Density Interconnects]/blog/pcb-copper-plating-electroless-vs-electrolytic-hdi-vias/)
• [PCB Via Reliability Testing: IST, Thermal Cycling, and IPC-6012 Compliance for Microvias]/blog/pcb-via-reliability-testing/)
• HDI PCB Manufacturing