High-Step HDI PCB with Staggered Vias

Project Overview

A semiconductor module company required an ultra-high-density interconnect PCB for their next-generation AIoT system-on-module. The module integrated a high-pin-count processor, DDR5 memory, and multiple high-speed interfaces in a compact 40x50mm form factor, requiring the most advanced HDI manufacturing capabilities.

Challenge

• Extreme density: 1200+ connections in a 40x50mm area required 10+ sequential HDI buildup steps with staggered microvia construction - pushing beyond conventional HDI capabilities.
• Ultra-fine features: 3/3 mil (75um) trace width and spacing with 4mil (100um) laser-drilled microvias, operating at the limits of current PCB manufacturing technology.
• Reliability at scale: Staggered microvia reliability across 10+ buildup layers required careful process control to prevent microvia cracking under thermal cycling.
• Impedance uniformity: High-speed DDR5 and PCIe signals required +/-5% impedance tolerance maintained across all HDI layers despite varying dielectric thicknesses in the buildup.

Solution

• Advanced HDI process: 10+ step sequential buildup with staggered (not stacked) microvias for maximum reliability. Each microvia layer processed with optimized laser parameters for clean hole formation in thin dielectric.
• Process monitoring: Real-time impedance monitoring with test coupons on every panel. Cross-section analysis at each buildup stage to verify microvia quality before proceeding to the next layer.
• Material selection: Low-loss, low-CTE prepreg materials selected to minimize Z-axis expansion during thermal cycling, reducing stress on microvia interconnections.
• Surface finish: Immersion gold (ENIG) with tightly controlled nickel thickness (3-5um) and gold thickness (0.05-0.1um) for reliable wire bonding and solder attachment.

PCB Specifications

Results

• 100% microvia reliability verified through 1000-cycle thermal shock testing (-55C to +125C)
• All high-speed channels passed eye diagram testing at full DDR5 and PCIe Gen5 data rates
• Achieved 95%+ yield on production panels, exceptional for 10+ step HDI
• Enabled customer to achieve 40% smaller module form factor vs previous generation